[llvm] 6f7cd16 - [AMDGPU] Fix v3f16 handling for getresinfo
Sebastian Neubauer via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 07:15:06 PDT 2020
Author: Sebastian Neubauer
Date: 2020-09-24T16:03:02+02:00
New Revision: 6f7cd16d297155332ff2b4c7efb01ca592eb7753
URL: https://github.com/llvm/llvm-project/commit/6f7cd16d297155332ff2b4c7efb01ca592eb7753
DIFF: https://github.com/llvm/llvm-project/commit/6f7cd16d297155332ff2b4c7efb01ca592eb7753.diff
LOG: [AMDGPU] Fix v3f16 handling for getresinfo
v3f32 should not be expanded to v4f32. getresinfo with a dmask of 7
created an image sample with a v3f32 return value, which was bitcasted
to a v4f32 in constructRetValue.
Differential Revision: https://reviews.llvm.org/D88206
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 710014f141b1..e3646d329118 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5877,7 +5877,8 @@ static SDValue constructRetValue(SelectionDAG &DAG,
Data = DAG.getNode(ISD::TRUNCATE, DL, ReqRetVT.changeTypeToInteger(), Data);
} else {
// We need to widen the return vector to a legal type
- if ((ReqRetVT.getVectorNumElements() % 2) == 1) {
+ if ((ReqRetVT.getVectorNumElements() % 2) == 1 &&
+ ReqRetVT.getVectorElementType().getSizeInBits() == 16) {
LegalReqRetVT =
EVT::getVectorVT(*DAG.getContext(), ReqRetVT.getVectorElementType(),
ReqRetVT.getVectorNumElements() + 1);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
index 6b975309cb33..527a8fb4369d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
@@ -387,6 +387,150 @@ main_body:
ret <4 x float> %v
}
+define amdgpu_ps <3 x float> @getresinfo_dmask7(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %mip) {
+; GFX6-LABEL: getresinfo_dmask7:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s3
+; GFX6-NEXT: s_mov_b32 s2, s4
+; GFX6-NEXT: s_mov_b32 s3, s5
+; GFX6-NEXT: s_mov_b32 s4, s6
+; GFX6-NEXT: s_mov_b32 s5, s7
+; GFX6-NEXT: s_mov_b32 s6, s8
+; GFX6-NEXT: s_mov_b32 s7, s9
+; GFX6-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 unorm
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: getresinfo_dmask7:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 unorm
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: getresinfo_dmask7:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: ; implicit-def: $vcc_hi
+; GFX10-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+main_body:
+ %r = call <3 x float> @llvm.amdgcn.image.getresinfo.1d.v3f32.i32(i32 7, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+ ret <3 x float> %r
+}
+
+define amdgpu_ps <2 x float> @getresinfo_dmask3(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %mip) {
+; GFX6-LABEL: getresinfo_dmask3:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s3
+; GFX6-NEXT: s_mov_b32 s2, s4
+; GFX6-NEXT: s_mov_b32 s3, s5
+; GFX6-NEXT: s_mov_b32 s4, s6
+; GFX6-NEXT: s_mov_b32 s5, s7
+; GFX6-NEXT: s_mov_b32 s6, s8
+; GFX6-NEXT: s_mov_b32 s7, s9
+; GFX6-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 unorm
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: getresinfo_dmask3:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 unorm
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: getresinfo_dmask3:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: ; implicit-def: $vcc_hi
+; GFX10-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+main_body:
+ %r = call <2 x float> @llvm.amdgcn.image.getresinfo.1d.v2f32.i32(i32 3, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+ ret <2 x float> %r
+}
+
+define amdgpu_ps float @getresinfo_dmask1(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %mip) {
+; GFX6-LABEL: getresinfo_dmask1:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s3
+; GFX6-NEXT: s_mov_b32 s2, s4
+; GFX6-NEXT: s_mov_b32 s3, s5
+; GFX6-NEXT: s_mov_b32 s4, s6
+; GFX6-NEXT: s_mov_b32 s5, s7
+; GFX6-NEXT: s_mov_b32 s6, s8
+; GFX6-NEXT: s_mov_b32 s7, s9
+; GFX6-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 unorm
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: getresinfo_dmask1:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 unorm
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: getresinfo_dmask1:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: ; implicit-def: $vcc_hi
+; GFX10-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+main_body:
+ %r = call float @llvm.amdgcn.image.getresinfo.1d.f32.i32(i32 1, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+ ret float %r
+}
+
define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %mip) {
; GFX6-LABEL: getresinfo_dmask0:
; GFX6: ; %bb.0: ; %main_body
@@ -406,6 +550,9 @@ main_body:
}
declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <3 x float> @llvm.amdgcn.image.getresinfo.1d.v3f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <2 x float> @llvm.amdgcn.image.getresinfo.1d.v2f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
+declare float @llvm.amdgcn.image.getresinfo.1d.f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
declare <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
declare <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
declare <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
index 5153c6f1eb2d..ca5a8180989d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
@@ -3167,6 +3167,198 @@ main_body:
ret void
}
+define amdgpu_ps <3 x float> @getresinfo_dmask7(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %mip) {
+; GFX6-LABEL: getresinfo_dmask7:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s3
+; GFX6-NEXT: s_mov_b32 s2, s4
+; GFX6-NEXT: s_mov_b32 s3, s5
+; GFX6-NEXT: s_mov_b32 s4, s6
+; GFX6-NEXT: s_mov_b32 s5, s7
+; GFX6-NEXT: s_mov_b32 s6, s8
+; GFX6-NEXT: s_mov_b32 s7, s9
+; GFX6-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 unorm
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: getresinfo_dmask7:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 unorm
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: ; return to shader part epilog
+;
+; VERDE-LABEL: getresinfo_dmask7:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 unorm
+; VERDE-NEXT: s_waitcnt vmcnt(0)
+; VERDE-NEXT: ; return to shader part epilog
+;
+; FIJI-LABEL: getresinfo_dmask7:
+; FIJI: ; %bb.0: ; %main_body
+; FIJI-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 unorm
+; FIJI-NEXT: s_waitcnt vmcnt(0)
+; FIJI-NEXT: ; return to shader part epilog
+;
+; GFX6789-LABEL: getresinfo_dmask7:
+; GFX6789: ; %bb.0: ; %main_body
+; GFX6789-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 unorm
+; GFX6789-NEXT: s_waitcnt vmcnt(0)
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; NOPRT-LABEL: getresinfo_dmask7:
+; NOPRT: ; %bb.0: ; %main_body
+; NOPRT-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 unorm
+; NOPRT-NEXT: s_waitcnt vmcnt(0)
+; NOPRT-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: getresinfo_dmask7:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x17,0x38,0xf0,0x00,0x00,0x00,0x00]
+; GFX10-NEXT: ; implicit-def: $vcc_hi
+; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
+; GFX10-NEXT: ; return to shader part epilog
+main_body:
+ %r = call <3 x float> @llvm.amdgcn.image.getresinfo.1d.v3f32.i32(i32 7, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+ ret <3 x float> %r
+}
+
+define amdgpu_ps <2 x float> @getresinfo_dmask3(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %mip) {
+; GFX6-LABEL: getresinfo_dmask3:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s3
+; GFX6-NEXT: s_mov_b32 s2, s4
+; GFX6-NEXT: s_mov_b32 s3, s5
+; GFX6-NEXT: s_mov_b32 s4, s6
+; GFX6-NEXT: s_mov_b32 s5, s7
+; GFX6-NEXT: s_mov_b32 s6, s8
+; GFX6-NEXT: s_mov_b32 s7, s9
+; GFX6-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 unorm
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: getresinfo_dmask3:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 unorm
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: ; return to shader part epilog
+;
+; VERDE-LABEL: getresinfo_dmask3:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 unorm
+; VERDE-NEXT: s_waitcnt vmcnt(0)
+; VERDE-NEXT: ; return to shader part epilog
+;
+; FIJI-LABEL: getresinfo_dmask3:
+; FIJI: ; %bb.0: ; %main_body
+; FIJI-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 unorm
+; FIJI-NEXT: s_waitcnt vmcnt(0)
+; FIJI-NEXT: ; return to shader part epilog
+;
+; GFX6789-LABEL: getresinfo_dmask3:
+; GFX6789: ; %bb.0: ; %main_body
+; GFX6789-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 unorm
+; GFX6789-NEXT: s_waitcnt vmcnt(0)
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; NOPRT-LABEL: getresinfo_dmask3:
+; NOPRT: ; %bb.0: ; %main_body
+; NOPRT-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 unorm
+; NOPRT-NEXT: s_waitcnt vmcnt(0)
+; NOPRT-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: getresinfo_dmask3:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x13,0x38,0xf0,0x00,0x00,0x00,0x00]
+; GFX10-NEXT: ; implicit-def: $vcc_hi
+; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
+; GFX10-NEXT: ; return to shader part epilog
+main_body:
+ %r = call <2 x float> @llvm.amdgcn.image.getresinfo.1d.v2f32.i32(i32 3, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+ ret <2 x float> %r
+}
+
+define amdgpu_ps float @getresinfo_dmask1(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %mip) {
+; GFX6-LABEL: getresinfo_dmask1:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s3
+; GFX6-NEXT: s_mov_b32 s2, s4
+; GFX6-NEXT: s_mov_b32 s3, s5
+; GFX6-NEXT: s_mov_b32 s4, s6
+; GFX6-NEXT: s_mov_b32 s5, s7
+; GFX6-NEXT: s_mov_b32 s6, s8
+; GFX6-NEXT: s_mov_b32 s7, s9
+; GFX6-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 unorm
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: getresinfo_dmask1:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: s_mov_b32 s0, s2
+; GFX8-NEXT: s_mov_b32 s1, s3
+; GFX8-NEXT: s_mov_b32 s2, s4
+; GFX8-NEXT: s_mov_b32 s3, s5
+; GFX8-NEXT: s_mov_b32 s4, s6
+; GFX8-NEXT: s_mov_b32 s5, s7
+; GFX8-NEXT: s_mov_b32 s6, s8
+; GFX8-NEXT: s_mov_b32 s7, s9
+; GFX8-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 unorm
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: ; return to shader part epilog
+;
+; VERDE-LABEL: getresinfo_dmask1:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 unorm
+; VERDE-NEXT: s_waitcnt vmcnt(0)
+; VERDE-NEXT: ; return to shader part epilog
+;
+; FIJI-LABEL: getresinfo_dmask1:
+; FIJI: ; %bb.0: ; %main_body
+; FIJI-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 unorm
+; FIJI-NEXT: s_waitcnt vmcnt(0)
+; FIJI-NEXT: ; return to shader part epilog
+;
+; GFX6789-LABEL: getresinfo_dmask1:
+; GFX6789: ; %bb.0: ; %main_body
+; GFX6789-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 unorm
+; GFX6789-NEXT: s_waitcnt vmcnt(0)
+; GFX6789-NEXT: ; return to shader part epilog
+;
+; NOPRT-LABEL: getresinfo_dmask1:
+; NOPRT: ; %bb.0: ; %main_body
+; NOPRT-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 unorm
+; NOPRT-NEXT: s_waitcnt vmcnt(0)
+; NOPRT-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: getresinfo_dmask1:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x11,0x38,0xf0,0x00,0x00,0x00,0x00]
+; GFX10-NEXT: ; implicit-def: $vcc_hi
+; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
+; GFX10-NEXT: ; return to shader part epilog
+main_body:
+ %r = call float @llvm.amdgcn.image.getresinfo.1d.f32.i32(i32 1, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
+ ret float %r
+}
+
define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %mip) #0 {
; VERDE-LABEL: getresinfo_dmask0:
; VERDE: ; %bb.0: ; %main_body
@@ -3354,6 +3546,9 @@ declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float>, i32, i3
declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float>, i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #0
declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
+declare <3 x float> @llvm.amdgcn.image.getresinfo.1d.v3f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
+declare <2 x float> @llvm.amdgcn.image.getresinfo.1d.v2f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
+declare float @llvm.amdgcn.image.getresinfo.1d.f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #1
declare <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
declare <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
declare <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
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