[PATCH] D85653: [GlobalISel][AMDGPU] Lower G_SMULH/G_UMULH

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 22 07:13:10 PDT 2020


arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:597
+  if (ST.hasVOP3PInsts()) {
+    Mulh.clampMaxNumElements(0, S8, 2).lowerFor({V2S8});
+  }
----------------
Put the actions on separate lines


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:600
+
+  Mulh.scalarize(0).lower();
 
----------------
Separate lines


================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir:610
+    %13:_(s8), %14:_(s8), %15:_(s8), %16:_(s8) = G_UNMERGE_VALUES %12:_(<4 x s8>)
+    S_ENDPGM 0, implicit %13:_(s8), implicit %14:_(s8), implicit %15:_(s8), implicit %16:_(s8)
+...
----------------
Shouldn't use implicit uses of s8 values. I'm trying to fix implicit uses with illegal register types because we can't ultimately legalize these


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85653/new/

https://reviews.llvm.org/D85653



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