[llvm] 534f6e1 - [PeepholeOptimizer] Enhance the redundant COPY elimination.
Michael Liao via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 07:11:49 PDT 2020
Author: Michael Liao
Date: 2020-09-22T10:11:37-04:00
New Revision: 534f6e171808cfe9f3f9e3de7e754715d038c409
URL: https://github.com/llvm/llvm-project/commit/534f6e171808cfe9f3f9e3de7e754715d038c409
DIFF: https://github.com/llvm/llvm-project/commit/534f6e171808cfe9f3f9e3de7e754715d038c409.diff
LOG: [PeepholeOptimizer] Enhance the redundant COPY elimination.
- Eliminate redundant COPYs from the same register & subregister pair.
Differential Revision: https://reviews.llvm.org/D87939
Added:
llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
Modified:
llvm/lib/CodeGen/PeepholeOptimizer.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index ed2a50e90ffe..ca9e3cd25caa 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -215,11 +215,11 @@ namespace {
RecurrenceCycle &RC);
/// If copy instruction \p MI is a virtual register copy, track it in
- /// the set \p CopySrcRegs and \p CopyMIs. If this virtual register was
- /// previously seen as a copy, replace the uses of this copy with the
- /// previously seen copy's destination register.
- bool foldRedundantCopy(MachineInstr &MI, SmallSet<Register, 4> &CopySrcRegs,
- DenseMap<Register, MachineInstr *> &CopyMIs);
+ /// the set \p CopyMIs. If this virtual register was previously seen as a
+ /// copy, replace the uses of this copy with the previously seen copy's
+ /// destination register.
+ bool foldRedundantCopy(MachineInstr &MI,
+ DenseMap<RegSubRegPair, MachineInstr *> &CopyMIs);
/// Is the register \p Reg a non-allocatable physical register?
bool isNAPhysCopy(Register Reg);
@@ -1392,11 +1392,11 @@ bool PeepholeOptimizer::foldImmediate(
//
// Should replace %2 uses with %1:sub1
bool PeepholeOptimizer::foldRedundantCopy(
- MachineInstr &MI, SmallSet<Register, 4> &CopySrcRegs,
- DenseMap<Register, MachineInstr *> &CopyMIs) {
+ MachineInstr &MI, DenseMap<RegSubRegPair, MachineInstr *> &CopyMIs) {
assert(MI.isCopy() && "expected a COPY machine instruction");
Register SrcReg = MI.getOperand(1).getReg();
+ unsigned SrcSubReg = MI.getOperand(1).getSubReg();
if (!SrcReg.isVirtual())
return false;
@@ -1404,20 +1404,17 @@ bool PeepholeOptimizer::foldRedundantCopy(
if (!DstReg.isVirtual())
return false;
- if (CopySrcRegs.insert(SrcReg).second) {
+ RegSubRegPair SrcPair(SrcReg, SrcSubReg);
+
+ if (CopyMIs.insert(std::make_pair(SrcPair, &MI)).second) {
// First copy of this reg seen.
- CopyMIs.insert(std::make_pair(SrcReg, &MI));
return false;
}
- MachineInstr *PrevCopy = CopyMIs.find(SrcReg)->second;
+ MachineInstr *PrevCopy = CopyMIs.find(SrcPair)->second;
- unsigned SrcSubReg = MI.getOperand(1).getSubReg();
unsigned PrevSrcSubReg = PrevCopy->getOperand(1).getSubReg();
-
- // Can't replace
diff erent subregister extracts.
- if (SrcSubReg != PrevSrcSubReg)
- return false;
+ assert(SrcSubReg == PrevSrcSubReg && "Unexpected mismatching subreg!");
Register PrevDstReg = PrevCopy->getOperand(0).getReg();
@@ -1631,9 +1628,9 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
// without any intervening re-definition of $physreg.
DenseMap<Register, MachineInstr *> NAPhysToVirtMIs;
- // Set of virtual registers that are copied from.
- SmallSet<Register, 4> CopySrcRegs;
- DenseMap<Register, MachineInstr *> CopySrcMIs;
+ // Set of pairs of virtual registers and their subregs that are copied
+ // from.
+ DenseMap<RegSubRegPair, MachineInstr *> CopySrcMIs;
bool IsLoopHeader = MLI->isLoopHeader(&MBB);
@@ -1644,9 +1641,10 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
++MII;
LocalMIs.insert(MI);
- // Skip debug instructions. They should not affect this peephole optimization.
+ // Skip debug instructions. They should not affect this peephole
+ // optimization.
if (MI->isDebugInstr())
- continue;
+ continue;
if (MI->isPosition())
continue;
@@ -1721,9 +1719,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
continue;
}
- if (MI->isCopy() &&
- (foldRedundantCopy(*MI, CopySrcRegs, CopySrcMIs) ||
- foldRedundantNAPhysCopy(*MI, NAPhysToVirtMIs))) {
+ if (MI->isCopy() && (foldRedundantCopy(*MI, CopySrcMIs) ||
+ foldRedundantNAPhysCopy(*MI, NAPhysToVirtMIs))) {
LocalMIs.erase(MI);
LLVM_DEBUG(dbgs() << "Deleting redundant copy: " << *MI << "\n");
MI->eraseFromParent();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
index 28c0651b10fd..f8657345eb09 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
@@ -298,82 +298,67 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(<4 x i128> addrspace(
; GFX9-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v0
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX9-NEXT: v_add_u32_e32 v19, 1, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v3, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v5, s4
; GFX9-NEXT: v_mov_b32_e32 v6, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v17, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v18, v2, v4, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s6
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
; GFX9-NEXT: v_mov_b32_e32 v8, s7
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v6, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX9-NEXT: v_mov_b32_e32 v9, s8
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v8, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX9-NEXT: v_mov_b32_e32 v11, s10
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GFX9-NEXT: v_mov_b32_e32 v12, s11
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX9-NEXT: v_mov_b32_e32 v13, s12
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
; GFX9-NEXT: v_mov_b32_e32 v14, s13
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v14, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19
; GFX9-NEXT: v_mov_b32_e32 v15, s14
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX9-NEXT: v_mov_b32_e32 v16, s15
-; GFX9-NEXT: v_add_u32_e32 v2, 1, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v16, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: v_mov_b32_e32 v5, s2
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX9-NEXT: v_mov_b32_e32 v6, s3
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_mov_b32_e32 v7, s4
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
-; GFX9-NEXT: v_mov_b32_e32 v8, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GFX9-NEXT: v_mov_b32_e32 v9, s6
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
-; GFX9-NEXT: v_mov_b32_e32 v10, s7
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GFX9-NEXT: v_mov_b32_e32 v11, s8
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
-; GFX9-NEXT: v_mov_b32_e32 v12, s9
-; GFX9-NEXT: v_mov_b32_e32 v13, s10
-; GFX9-NEXT: v_mov_b32_e32 v5, s11
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
-; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_mov_b32_e32 v7, s13
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
@@ -383,82 +368,67 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(<4 x i128> addrspace(
; GFX8-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v3, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s2
-; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s3
; GFX8-NEXT: v_mov_b32_e32 v5, s4
; GFX8-NEXT: v_mov_b32_e32 v6, s5
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v17, v1, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v18, v2, v4, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX8-NEXT: v_mov_b32_e32 v7, s6
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
; GFX8-NEXT: v_mov_b32_e32 v8, s7
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v6, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX8-NEXT: v_mov_b32_e32 v9, s8
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GFX8-NEXT: v_mov_b32_e32 v10, s9
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX8-NEXT: v_mov_b32_e32 v11, s10
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GFX8-NEXT: v_mov_b32_e32 v12, s11
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX8-NEXT: v_mov_b32_e32 v13, s12
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
; GFX8-NEXT: v_mov_b32_e32 v14, s13
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v0, v14, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc
+; GFX8-NEXT: v_add_u32_e32 v19, vcc, 1, v0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19
; GFX8-NEXT: v_mov_b32_e32 v15, s14
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX8-NEXT: v_mov_b32_e32 v16, s15
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v16, vcc
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v2
-; GFX8-NEXT: v_mov_b32_e32 v4, s1
-; GFX8-NEXT: v_mov_b32_e32 v5, s2
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX8-NEXT: v_mov_b32_e32 v6, s3
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT: v_mov_b32_e32 v7, s4
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
-; GFX8-NEXT: v_mov_b32_e32 v8, s5
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GFX8-NEXT: v_mov_b32_e32 v9, s6
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
-; GFX8-NEXT: v_mov_b32_e32 v10, s7
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1]
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GFX8-NEXT: v_mov_b32_e32 v11, s8
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
-; GFX8-NEXT: v_mov_b32_e32 v12, s9
-; GFX8-NEXT: v_mov_b32_e32 v13, s10
-; GFX8-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
-; GFX8-NEXT: v_mov_b32_e32 v6, s12
-; GFX8-NEXT: v_mov_b32_e32 v7, s13
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
-; GFX8-NEXT: v_mov_b32_e32 v8, s14
-; GFX8-NEXT: v_mov_b32_e32 v9, s15
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: v_readfirstlane_b32 s2, v2
@@ -468,82 +438,67 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(<4 x i128> addrspace(
; GFX7-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 1, v0
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX7-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, s0
-; GFX7-NEXT: v_mov_b32_e32 v1, s2
-; GFX7-NEXT: v_mov_b32_e32 v0, s1
+; GFX7-NEXT: v_mov_b32_e32 v1, s0
+; GFX7-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: v_mov_b32_e32 v4, s3
; GFX7-NEXT: v_mov_b32_e32 v5, s4
; GFX7-NEXT: v_mov_b32_e32 v6, s5
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v17, v1, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v18, v2, v4, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX7-NEXT: v_mov_b32_e32 v7, s6
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
; GFX7-NEXT: v_mov_b32_e32 v8, s7
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v5, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v6, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX7-NEXT: v_mov_b32_e32 v9, s8
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GFX7-NEXT: v_mov_b32_e32 v10, s9
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v7, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v8, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX7-NEXT: v_mov_b32_e32 v11, s10
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GFX7-NEXT: v_mov_b32_e32 v12, s11
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX7-NEXT: v_mov_b32_e32 v13, s12
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
; GFX7-NEXT: v_mov_b32_e32 v14, s13
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v0, v14, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
+; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc
+; GFX7-NEXT: v_add_i32_e32 v19, vcc, 1, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19
; GFX7-NEXT: v_mov_b32_e32 v15, s14
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX7-NEXT: v_mov_b32_e32 v16, s15
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v4, v16, vcc
-; GFX7-NEXT: v_add_i32_e32 v2, vcc, 1, v2
-; GFX7-NEXT: v_mov_b32_e32 v4, s1
-; GFX7-NEXT: v_mov_b32_e32 v5, s2
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX7-NEXT: v_mov_b32_e32 v6, s3
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX7-NEXT: v_mov_b32_e32 v7, s4
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
-; GFX7-NEXT: v_mov_b32_e32 v8, s5
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GFX7-NEXT: v_mov_b32_e32 v9, s6
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
-; GFX7-NEXT: v_mov_b32_e32 v10, s7
+; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19
+; GFX7-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1]
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc
+; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1]
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GFX7-NEXT: v_mov_b32_e32 v11, s8
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
-; GFX7-NEXT: v_mov_b32_e32 v12, s9
-; GFX7-NEXT: v_mov_b32_e32 v13, s10
-; GFX7-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
-; GFX7-NEXT: v_mov_b32_e32 v6, s12
-; GFX7-NEXT: v_mov_b32_e32 v7, s13
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
-; GFX7-NEXT: v_mov_b32_e32 v8, s14
-; GFX7-NEXT: v_mov_b32_e32 v9, s15
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v8, vcc
-; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
; GFX7-NEXT: v_readfirstlane_b32 s1, v1
; GFX7-NEXT: v_readfirstlane_b32 s2, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
index f188fc05f363..1d56af554190 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
@@ -236,6 +236,7 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: s_subb_u32 s5, 0, s11
+; CHECK-NEXT: v_mov_b32_e32 v6, s11
; CHECK-NEXT: v_mul_lo_u32 v2, s5, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s3, v1
; CHECK-NEXT: v_mul_hi_u32 v5, s3, v0
@@ -244,21 +245,21 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_mul_lo_u32 v3, v1, v4
; CHECK-NEXT: v_mul_lo_u32 v5, v0, v2
-; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4
+; CHECK-NEXT: v_mul_hi_u32 v7, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
@@ -267,87 +268,86 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_addc_u32_e64 v3, s[0:1], v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v4, s5, v0
; CHECK-NEXT: v_mul_lo_u32 v5, s3, v3
-; CHECK-NEXT: v_mul_hi_u32 v7, s3, v0
-; CHECK-NEXT: v_mul_lo_u32 v6, s3, v0
+; CHECK-NEXT: v_mul_hi_u32 v8, s3, v0
+; CHECK-NEXT: v_mul_lo_u32 v7, s3, v0
; CHECK-NEXT: v_add_i32_e64 v1, s[0:1], v1, v2
; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v5
-; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v7
-; CHECK-NEXT: v_mul_lo_u32 v5, v3, v6
-; CHECK-NEXT: v_mul_lo_u32 v7, v0, v4
-; CHECK-NEXT: v_mul_hi_u32 v2, v0, v6
-; CHECK-NEXT: v_mul_hi_u32 v6, v3, v6
-; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
+; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v8
+; CHECK-NEXT: v_mul_lo_u32 v5, v3, v7
+; CHECK-NEXT: v_mul_lo_u32 v8, v0, v4
+; CHECK-NEXT: v_mul_hi_u32 v2, v0, v7
+; CHECK-NEXT: v_mul_hi_u32 v7, v3, v7
+; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; CHECK-NEXT: v_mul_lo_u32 v5, v3, v4
-; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v7, v2
-; CHECK-NEXT: v_mul_hi_u32 v7, v0, v4
+; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v8, v2
+; CHECK-NEXT: v_mul_hi_u32 v8, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v3, v3, v4
-; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
-; CHECK-NEXT: v_add_i32_e64 v6, s[0:1], v6, v7
+; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
+; CHECK-NEXT: v_add_i32_e64 v7, s[0:1], v7, v8
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v6, v5
+; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v7, v5
; CHECK-NEXT: v_add_i32_e64 v3, s[0:1], v3, v4
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, s13, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s12, v1
-; CHECK-NEXT: v_mul_hi_u32 v4, s12, v0
+; CHECK-NEXT: v_mul_hi_u32 v5, s12, v0
; CHECK-NEXT: v_mul_hi_u32 v0, s13, v0
+; CHECK-NEXT: v_mov_b32_e32 v4, s13
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_mul_lo_u32 v4, s13, v1
+; CHECK-NEXT: v_mul_lo_u32 v5, s13, v1
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_mul_hi_u32 v3, s12, v1
; CHECK-NEXT: v_mul_hi_u32 v1, s13, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v4, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CHECK-NEXT: v_mul_lo_u32 v2, s11, v0
; CHECK-NEXT: v_mul_lo_u32 v1, s10, v1
-; CHECK-NEXT: v_mul_hi_u32 v4, s10, v0
+; CHECK-NEXT: v_mul_hi_u32 v5, s10, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s10, v0
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v4
-; CHECK-NEXT: v_mov_b32_e32 v2, s13
-; CHECK-NEXT: v_sub_i32_e32 v3, vcc, s12, v3
-; CHECK-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v1, vcc
+; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v5
+; CHECK-NEXT: v_sub_i32_e32 v2, vcc, s12, v3
+; CHECK-NEXT: v_subb_u32_e64 v3, s[0:1], v4, v1, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[0:1], s13, v1
-; CHECK-NEXT: v_mov_b32_e32 v4, s11
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v2
-; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
+; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v3
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2
+; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s10, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v3
-; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s10, v3
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v3
+; CHECK-NEXT: v_cndmask_b32_e64 v3, v4, v5, s[0:1]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s11, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v2, v5, v6, s[0:1]
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, s11, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v4
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, 1, v4
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CHECK-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9]
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, s0, v0
@@ -1293,47 +1293,47 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v1, v4
; GISEL-NEXT: v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT: v_mul_hi_u32 v9, v0, v4
+; GISEL-NEXT: v_mul_hi_u32 v10, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4
+; GISEL-NEXT: v_mov_b32_e32 v9, s9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v9, v1, v5
+; GISEL-NEXT: v_mul_lo_u32 v10, v1, v5
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v7, s9, v4
; GISEL-NEXT: v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT: v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT: v_mul_hi_u32 v11, s8, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, s8, v4
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7
-; GISEL-NEXT: v_mov_b32_e32 v7, s9
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v7, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v0
; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v10, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GISEL-NEXT: s_add_u32 s4, s10, 0
@@ -1342,15 +1342,15 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1
; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, 1, v7
+; GISEL-NEXT: v_add_i32_e32 v1, vcc, 1, v8
; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GISEL-NEXT: s_addc_u32 s5, 0, 0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s6
@@ -1362,141 +1362,141 @@ define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GISEL-NEXT: s_subb_u32 s9, 0, s7
-; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3
+; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GISEL-NEXT: v_trunc_f32_e32 v5, v5
; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
-; GISEL-NEXT: v_mul_lo_u32 v8, s9, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5
-; GISEL-NEXT: v_mul_hi_u32 v11, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v10, s8, v4
-; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
+; GISEL-NEXT: v_mul_lo_u32 v7, s9, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, s8, v5
+; GISEL-NEXT: v_mul_hi_u32 v10, s8, v4
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v3
+; GISEL-NEXT: v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT: v_mul_lo_u32 v8, v5, v9
+; GISEL-NEXT: v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT: v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v9, v5, v9
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT: v_mul_lo_u32 v9, v5, v10
-; GISEL-NEXT: v_mul_lo_u32 v11, v4, v8
-; GISEL-NEXT: v_mul_hi_u32 v12, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v10, v5, v10
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v7
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v5, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v11, v5, v7
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_mul_hi_u32 v10, v4, v7
+; GISEL-NEXT: v_mul_hi_u32 v7, v5, v7
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT: v_mul_hi_u32 v11, v4, v8
-; GISEL-NEXT: v_mul_hi_u32 v8, v5, v8
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
-; GISEL-NEXT: v_addc_u32_e64 v9, s[4:5], v5, v8, vcc
-; GISEL-NEXT: v_mul_lo_u32 v10, s9, v4
-; GISEL-NEXT: v_mul_lo_u32 v11, s8, v9
-; GISEL-NEXT: v_mul_hi_u32 v13, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v12, s8, v4
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v8
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
-; GISEL-NEXT: v_mul_lo_u32 v11, v9, v12
-; GISEL-NEXT: v_mul_lo_u32 v13, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v8, v4, v12
-; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT: v_mul_lo_u32 v11, v9, v10
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v13, v8
-; GISEL-NEXT: v_mul_hi_u32 v13, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v9, v9, v10
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
+; GISEL-NEXT: v_mul_lo_u32 v9, s9, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, s8, v8
+; GISEL-NEXT: v_mul_hi_u32 v12, s8, v4
+; GISEL-NEXT: v_mul_lo_u32 v11, s8, v4
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v7
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
+; GISEL-NEXT: v_mul_lo_u32 v12, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v7, v4, v11
+; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v6
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5]
+; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7
+; GISEL-NEXT: v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v12, v11
-; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10
+; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, v2, v5
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT: v_mul_hi_u32 v6, v2, v4
+; GISEL-NEXT: v_mul_lo_u32 v7, v3, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, v2, v5
+; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v5
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
-; GISEL-NEXT: v_mul_hi_u32 v9, v2, v5
+; GISEL-NEXT: v_mov_b32_e32 v9, s7
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v10, v3, v5
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_mul_hi_u32 v8, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_mul_lo_u32 v6, s7, v4
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT: v_mul_lo_u32 v7, s7, v4
; GISEL-NEXT: v_mul_lo_u32 v8, s6, v5
-; GISEL-NEXT: v_mul_hi_u32 v10, s6, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, s6, v4
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
-; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v6, vcc
-; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v6
-; GISEL-NEXT: v_mov_b32_e32 v6, s7
+; GISEL-NEXT: v_mul_hi_u32 v11, s6, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, s6, v4
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v10
+; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
+; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v2
; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, s6, v2
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v10, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s6, v2
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, s7, v3
; GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v6
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v8
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v7
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v6
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_sdiv_v2i64_pow2k_denom:
@@ -2016,47 +2016,47 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v1, v4
; GISEL-NEXT: v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT: v_mul_hi_u32 v9, v0, v4
+; GISEL-NEXT: v_mul_hi_u32 v10, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4
+; GISEL-NEXT: v_mov_b32_e32 v9, s9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v9, v1, v5
+; GISEL-NEXT: v_mul_lo_u32 v10, v1, v5
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v7, s9, v4
; GISEL-NEXT: v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT: v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT: v_mul_hi_u32 v11, s8, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, s8, v4
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7
-; GISEL-NEXT: v_mov_b32_e32 v7, s9
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v7, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v0
; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v10, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GISEL-NEXT: s_add_u32 s4, s10, 0
@@ -2065,15 +2065,15 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1
; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, 1, v7
+; GISEL-NEXT: v_add_i32_e32 v1, vcc, 1, v8
; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GISEL-NEXT: s_addc_u32 s5, 0, 0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s6
@@ -2085,141 +2085,141 @@ define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GISEL-NEXT: s_subb_u32 s9, 0, s7
-; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3
+; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GISEL-NEXT: v_trunc_f32_e32 v5, v5
; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
-; GISEL-NEXT: v_mul_lo_u32 v8, s9, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5
-; GISEL-NEXT: v_mul_hi_u32 v11, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v10, s8, v4
-; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
+; GISEL-NEXT: v_mul_lo_u32 v7, s9, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, s8, v5
+; GISEL-NEXT: v_mul_hi_u32 v10, s8, v4
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v3
+; GISEL-NEXT: v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT: v_mul_lo_u32 v8, v5, v9
+; GISEL-NEXT: v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT: v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v9, v5, v9
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT: v_mul_lo_u32 v9, v5, v10
-; GISEL-NEXT: v_mul_lo_u32 v11, v4, v8
-; GISEL-NEXT: v_mul_hi_u32 v12, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v10, v5, v10
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v7
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v5, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v11, v5, v7
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_mul_hi_u32 v10, v4, v7
+; GISEL-NEXT: v_mul_hi_u32 v7, v5, v7
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT: v_mul_hi_u32 v11, v4, v8
-; GISEL-NEXT: v_mul_hi_u32 v8, v5, v8
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
-; GISEL-NEXT: v_addc_u32_e64 v9, s[4:5], v5, v8, vcc
-; GISEL-NEXT: v_mul_lo_u32 v10, s9, v4
-; GISEL-NEXT: v_mul_lo_u32 v11, s8, v9
-; GISEL-NEXT: v_mul_hi_u32 v13, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v12, s8, v4
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v8
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
-; GISEL-NEXT: v_mul_lo_u32 v11, v9, v12
-; GISEL-NEXT: v_mul_lo_u32 v13, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v8, v4, v12
-; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT: v_mul_lo_u32 v11, v9, v10
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v13, v8
-; GISEL-NEXT: v_mul_hi_u32 v13, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v9, v9, v10
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
+; GISEL-NEXT: v_mul_lo_u32 v9, s9, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, s8, v8
+; GISEL-NEXT: v_mul_hi_u32 v12, s8, v4
+; GISEL-NEXT: v_mul_lo_u32 v11, s8, v4
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v7
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
+; GISEL-NEXT: v_mul_lo_u32 v12, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v7, v4, v11
+; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v6
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5]
+; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7
+; GISEL-NEXT: v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v12, v11
-; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10
+; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, v2, v5
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT: v_mul_hi_u32 v6, v2, v4
+; GISEL-NEXT: v_mul_lo_u32 v7, v3, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, v2, v5
+; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v5
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
-; GISEL-NEXT: v_mul_hi_u32 v9, v2, v5
+; GISEL-NEXT: v_mov_b32_e32 v9, s7
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v10, v3, v5
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_mul_hi_u32 v8, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_mul_lo_u32 v6, s7, v4
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT: v_mul_lo_u32 v7, s7, v4
; GISEL-NEXT: v_mul_lo_u32 v8, s6, v5
-; GISEL-NEXT: v_mul_hi_u32 v10, s6, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, s6, v4
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
-; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v6, vcc
-; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v6
-; GISEL-NEXT: v_mov_b32_e32 v6, s7
+; GISEL-NEXT: v_mul_hi_u32 v11, s6, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, s6, v4
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v10
+; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
+; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v2
; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, s6, v2
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v10, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s6, v2
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, s7, v3
; GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v6
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v8
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v7
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v6
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_sdiv_v2i64_oddk_denom:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
index f769b826b1ea..9de42fa16e49 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -232,6 +232,7 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: s_subb_u32 s5, 0, s11
+; CHECK-NEXT: v_mov_b32_e32 v6, s11
; CHECK-NEXT: v_mul_lo_u32 v2, s5, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s3, v1
; CHECK-NEXT: v_mul_hi_u32 v5, s3, v0
@@ -240,21 +241,21 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_mul_lo_u32 v3, v1, v4
; CHECK-NEXT: v_mul_lo_u32 v5, v0, v2
-; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4
+; CHECK-NEXT: v_mul_hi_u32 v7, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2
+; CHECK-NEXT: v_mul_lo_u32 v7, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
@@ -263,52 +264,53 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_addc_u32_e64 v3, s[0:1], v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v4, s5, v0
; CHECK-NEXT: v_mul_lo_u32 v5, s3, v3
-; CHECK-NEXT: v_mul_hi_u32 v7, s3, v0
-; CHECK-NEXT: v_mul_lo_u32 v6, s3, v0
+; CHECK-NEXT: v_mul_hi_u32 v8, s3, v0
+; CHECK-NEXT: v_mul_lo_u32 v7, s3, v0
; CHECK-NEXT: v_add_i32_e64 v1, s[0:1], v1, v2
; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v5
-; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v7
-; CHECK-NEXT: v_mul_lo_u32 v5, v3, v6
-; CHECK-NEXT: v_mul_lo_u32 v7, v0, v4
-; CHECK-NEXT: v_mul_hi_u32 v2, v0, v6
-; CHECK-NEXT: v_mul_hi_u32 v6, v3, v6
-; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
+; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v8
+; CHECK-NEXT: v_mul_lo_u32 v5, v3, v7
+; CHECK-NEXT: v_mul_lo_u32 v8, v0, v4
+; CHECK-NEXT: v_mul_hi_u32 v2, v0, v7
+; CHECK-NEXT: v_mul_hi_u32 v7, v3, v7
+; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; CHECK-NEXT: v_mul_lo_u32 v5, v3, v4
-; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v7, v2
-; CHECK-NEXT: v_mul_hi_u32 v7, v0, v4
+; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v8, v2
+; CHECK-NEXT: v_mul_hi_u32 v8, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v3, v3, v4
-; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v6
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
-; CHECK-NEXT: v_add_i32_e64 v6, s[0:1], v6, v7
+; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
+; CHECK-NEXT: v_add_i32_e64 v7, s[0:1], v7, v8
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v6, v5
+; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v7, v5
; CHECK-NEXT: v_add_i32_e64 v3, s[0:1], v3, v4
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, s9, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s8, v1
-; CHECK-NEXT: v_mul_hi_u32 v4, s8, v0
+; CHECK-NEXT: v_mul_hi_u32 v5, s8, v0
; CHECK-NEXT: v_mul_hi_u32 v0, s9, v0
+; CHECK-NEXT: v_mov_b32_e32 v4, s9
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT: v_mul_lo_u32 v4, s9, v1
+; CHECK-NEXT: v_mul_lo_u32 v5, s9, v1
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_mul_hi_u32 v3, s8, v1
; CHECK-NEXT: v_mul_hi_u32 v1, s9, v1
-; CHECK-NEXT: v_add_i32_e32 v0, vcc, v4, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v0, vcc, v5, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
@@ -319,21 +321,19 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_mul_hi_u32 v0, s10, v0
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; CHECK-NEXT: v_sub_i32_e32 v2, vcc, s8, v3
-; CHECK-NEXT: v_mov_b32_e32 v1, s9
-; CHECK-NEXT: v_subb_u32_e64 v1, s[0:1], v1, v0, vcc
+; CHECK-NEXT: v_sub_i32_e32 v1, vcc, s8, v3
+; CHECK-NEXT: v_subb_u32_e64 v2, s[0:1], v4, v0, vcc
; CHECK-NEXT: v_sub_i32_e64 v0, s[0:1], s9, v0
-; CHECK-NEXT: v_mov_b32_e32 v3, s11
-; CHECK-NEXT: v_subb_u32_e32 v0, vcc, v0, v3, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s10, v2
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v1
-; CHECK-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
+; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1]
+; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v1
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v1
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v2
+; CHECK-NEXT: v_subb_u32_e32 v0, vcc, v0, v6, vcc
+; CHECK-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1]
+; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s10, v1
+; CHECK-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s11, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v1, v4, v5, s[0:1]
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
@@ -342,8 +342,8 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s10, v3
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; CHECK-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, s6, v0
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
; CHECK-NEXT: s_mov_b32 s1, 0
@@ -1271,21 +1271,22 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v1, v4
; GISEL-NEXT: v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT: v_mul_hi_u32 v9, v0, v4
+; GISEL-NEXT: v_mul_hi_u32 v10, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4
+; GISEL-NEXT: v_mov_b32_e32 v9, s9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v9, v1, v5
+; GISEL-NEXT: v_mul_lo_u32 v10, v1, v5
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
@@ -1300,35 +1301,33 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v4
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT: v_mov_b32_e32 v4, s9
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
-; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s8, v0
-; GISEL-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v1, vcc
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s9, v9
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
+; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s8, v0
+; GISEL-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v1, vcc
+; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v8
+; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v7
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s9, v9
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5]
; GISEL-NEXT: s_add_u32 s4, s10, 0
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
; GISEL-NEXT: s_cselect_b32 s5, 1, 0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s8, v8
+; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, s8, v7
; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GISEL-NEXT: s_addc_u32 s5, 0, 0
; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s6
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s7
@@ -1338,141 +1337,142 @@ define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GISEL-NEXT: s_subb_u32 s9, 0, s7
-; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GISEL-NEXT: v_trunc_f32_e32 v5, v5
; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
-; GISEL-NEXT: v_mul_lo_u32 v8, s9, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5
-; GISEL-NEXT: v_mul_hi_u32 v11, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v10, s8, v4
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
+; GISEL-NEXT: v_mul_lo_u32 v7, s9, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, s8, v5
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
+; GISEL-NEXT: v_mul_hi_u32 v10, s8, v4
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v3
+; GISEL-NEXT: v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT: v_mul_lo_u32 v8, v5, v9
+; GISEL-NEXT: v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT: v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v9, v5, v9
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT: v_mul_lo_u32 v9, v5, v10
-; GISEL-NEXT: v_mul_lo_u32 v11, v4, v8
-; GISEL-NEXT: v_mul_hi_u32 v12, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v10, v5, v10
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v7
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v5, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v11, v5, v7
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_mul_hi_u32 v10, v4, v7
+; GISEL-NEXT: v_mul_hi_u32 v7, v5, v7
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT: v_mul_hi_u32 v11, v4, v8
-; GISEL-NEXT: v_mul_hi_u32 v8, v5, v8
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
-; GISEL-NEXT: v_addc_u32_e64 v9, s[4:5], v5, v8, vcc
-; GISEL-NEXT: v_mul_lo_u32 v10, s9, v4
-; GISEL-NEXT: v_mul_lo_u32 v11, s8, v9
-; GISEL-NEXT: v_mul_hi_u32 v13, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v12, s8, v4
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v8
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
-; GISEL-NEXT: v_mul_lo_u32 v11, v9, v12
-; GISEL-NEXT: v_mul_lo_u32 v13, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v8, v4, v12
-; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT: v_mul_lo_u32 v11, v9, v10
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v13, v8
-; GISEL-NEXT: v_mul_hi_u32 v13, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v9, v9, v10
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
+; GISEL-NEXT: v_mul_lo_u32 v9, s9, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, s8, v8
+; GISEL-NEXT: v_mul_hi_u32 v12, s8, v4
+; GISEL-NEXT: v_mul_lo_u32 v11, s8, v4
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v7
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
+; GISEL-NEXT: v_mul_lo_u32 v12, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v7, v4, v11
+; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v6
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5]
+; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7
+; GISEL-NEXT: v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v12, v11
-; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10
+; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, v2, v5
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT: v_mul_hi_u32 v6, v2, v4
+; GISEL-NEXT: v_mul_lo_u32 v7, v3, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, v2, v5
+; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v5
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
-; GISEL-NEXT: v_mul_hi_u32 v9, v2, v5
+; GISEL-NEXT: v_mov_b32_e32 v9, s7
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v10, v3, v5
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_mul_hi_u32 v8, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_mul_lo_u32 v6, s7, v4
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT: v_mul_lo_u32 v7, s7, v4
; GISEL-NEXT: v_mul_lo_u32 v5, s6, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s6, v4
; GISEL-NEXT: v_mul_hi_u32 v4, s6, v4
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT: v_mov_b32_e32 v4, s7
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v2
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5]
-; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s6, v2
-; GISEL-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v3, vcc
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v9
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
+; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s6, v2
+; GISEL-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
+; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v8
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v8
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s6, v8
+; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v7
+; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, s6, v7
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s7, v9
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5]
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v7
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v6
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_srem_v2i64_pow2k_denom:
@@ -1986,21 +1986,22 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v1, v4
; GISEL-NEXT: v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT: v_mul_hi_u32 v9, v0, v4
+; GISEL-NEXT: v_mul_hi_u32 v10, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4
+; GISEL-NEXT: v_mov_b32_e32 v9, s9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v9, v1, v5
+; GISEL-NEXT: v_mul_lo_u32 v10, v1, v5
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
@@ -2015,35 +2016,33 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v4
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT: v_mov_b32_e32 v4, s9
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
-; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s8, v0
-; GISEL-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v1, vcc
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s9, v9
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
+; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s8, v0
+; GISEL-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v1, vcc
+; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v8
+; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v7
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s9, v9
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5]
; GISEL-NEXT: s_add_u32 s4, s10, 0
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc
; GISEL-NEXT: s_cselect_b32 s5, 1, 0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s8, v8
+; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, s8, v7
; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GISEL-NEXT: s_addc_u32 s5, 0, 0
; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s6
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s7
@@ -2053,141 +2052,142 @@ define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GISEL-NEXT: s_subb_u32 s9, 0, s7
-; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GISEL-NEXT: v_trunc_f32_e32 v5, v5
; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
-; GISEL-NEXT: v_mul_lo_u32 v8, s9, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5
-; GISEL-NEXT: v_mul_hi_u32 v11, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v10, s8, v4
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
+; GISEL-NEXT: v_mul_lo_u32 v7, s9, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, s8, v5
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
+; GISEL-NEXT: v_mul_hi_u32 v10, s8, v4
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
+; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v3
+; GISEL-NEXT: v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT: v_mul_lo_u32 v8, v5, v9
+; GISEL-NEXT: v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT: v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v9, v5, v9
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT: v_mul_lo_u32 v9, v5, v10
-; GISEL-NEXT: v_mul_lo_u32 v11, v4, v8
-; GISEL-NEXT: v_mul_hi_u32 v12, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v10, v5, v10
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v7
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v5, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v11, v5, v7
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_mul_hi_u32 v10, v4, v7
+; GISEL-NEXT: v_mul_hi_u32 v7, v5, v7
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT: v_mul_hi_u32 v11, v4, v8
-; GISEL-NEXT: v_mul_hi_u32 v8, v5, v8
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
-; GISEL-NEXT: v_addc_u32_e64 v9, s[4:5], v5, v8, vcc
-; GISEL-NEXT: v_mul_lo_u32 v10, s9, v4
-; GISEL-NEXT: v_mul_lo_u32 v11, s8, v9
-; GISEL-NEXT: v_mul_hi_u32 v13, s8, v4
-; GISEL-NEXT: v_mul_lo_u32 v12, s8, v4
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v8
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
-; GISEL-NEXT: v_mul_lo_u32 v11, v9, v12
-; GISEL-NEXT: v_mul_lo_u32 v13, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v8, v4, v12
-; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT: v_mul_lo_u32 v11, v9, v10
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v13, v8
-; GISEL-NEXT: v_mul_hi_u32 v13, v4, v10
-; GISEL-NEXT: v_mul_hi_u32 v9, v9, v10
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
+; GISEL-NEXT: v_mul_lo_u32 v9, s9, v4
+; GISEL-NEXT: v_mul_lo_u32 v10, s8, v8
+; GISEL-NEXT: v_mul_hi_u32 v12, s8, v4
+; GISEL-NEXT: v_mul_lo_u32 v11, s8, v4
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v7
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
+; GISEL-NEXT: v_mul_lo_u32 v12, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v7, v4, v11
+; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v6
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
-; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5]
+; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7
+; GISEL-NEXT: v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v12, v11
-; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10
+; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4
-; GISEL-NEXT: v_mul_lo_u32 v9, v2, v5
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT: v_mul_hi_u32 v6, v2, v4
+; GISEL-NEXT: v_mul_lo_u32 v7, v3, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, v2, v5
+; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v5
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
-; GISEL-NEXT: v_mul_hi_u32 v9, v2, v5
+; GISEL-NEXT: v_mov_b32_e32 v9, s7
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT: v_mul_lo_u32 v10, v3, v5
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_mul_hi_u32 v8, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT: v_mul_lo_u32 v6, s7, v4
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT: v_mul_lo_u32 v7, s7, v4
; GISEL-NEXT: v_mul_lo_u32 v5, s6, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s6, v4
; GISEL-NEXT: v_mul_hi_u32 v4, s6, v4
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT: v_mov_b32_e32 v4, s7
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v2
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5]
-; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s6, v2
-; GISEL-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v3, vcc
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v9
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
+; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s6, v2
+; GISEL-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
+; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v8
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v8
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s6, v8
+; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v7
+; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, s6, v7
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s7, v9
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5]
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT: v_xor_b32_e32 v2, v2, v7
-; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
+; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v6
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_srem_v2i64_oddk_denom:
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll b/llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
new file mode 100644
index 000000000000..b574e5d98c40
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -o - %s | FileCheck %s
+
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
+target triple = "amdgcn-amd-amdhsa"
+
+; CHECK-LABEL: {{^}}t0:
+; CHECK: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]], s[4:5], 0x0
+; CHECK: v_mov_b32_e32 v{{[0-9]+}}, s[[PTR_HI]]
+; There should be no redundant copies from PTR_HI.
+; CHECK-NOT: v_mov_b32_e32 v{{[0-9]+}}, s[[PTR_HI]]
+define protected amdgpu_kernel void @t0(float addrspace(1)* %p, i32 %i0, i32 %j0, i32 %k0) {
+entry:
+ %0 = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %i = add i32 %0, %i0
+ %j = add i32 %0, %j0
+ %k = add i32 %0, %k0
+ %pi = getelementptr float, float addrspace(1)* %p, i32 %i
+ %vi = load float, float addrspace(1)* %pi
+ %pj = getelementptr float, float addrspace(1)* %p, i32 %j
+ %vj = load float, float addrspace(1)* %pj
+ %sum = fadd float %vi, %vj
+ %pk = getelementptr float, float addrspace(1)* %p, i32 %k
+ store float %sum, float addrspace(1)* %pk
+ ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll b/llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
index 4cbd89147722..4d9c6a9a540f 100644
--- a/llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
@@ -153,7 +153,9 @@ bb:
; GCN-LABEL: barrier_vmcnt_vscnt_flat_workgroup:
; GCN: flat_load_dword
-; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
+; GFX8_9: s_waitcnt lgkmcnt(0){{$}}
+; GFX8_9: s_waitcnt vmcnt(0){{$}}
+; GFX10: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GFX10: s_waitcnt_vscnt null, 0x0
; GCN-NEXT: s_barrier
define amdgpu_kernel void @barrier_vmcnt_vscnt_flat_workgroup(i32* %arg) {
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcvt16.ll b/llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
index c5421feb6c9d..98ee5fdd3f34 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
@@ -18,15 +18,15 @@ entry:
define arm_aapcs_vfpcc <8 x float> @fpext_8(<8 x half> %src1) {
; CHECK-LABEL: fpext_8:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov q2, q0
-; CHECK-NEXT: vcvtt.f32.f16 s3, s9
-; CHECK-NEXT: vcvtt.f32.f16 s7, s11
-; CHECK-NEXT: vcvtb.f32.f16 s2, s9
-; CHECK-NEXT: vcvtb.f32.f16 s6, s11
-; CHECK-NEXT: vcvtt.f32.f16 s1, s8
-; CHECK-NEXT: vcvtt.f32.f16 s5, s10
-; CHECK-NEXT: vcvtb.f32.f16 s0, s8
-; CHECK-NEXT: vcvtb.f32.f16 s4, s10
+; CHECK-NEXT: vcvtt.f32.f16 s11, s1
+; CHECK-NEXT: vcvtt.f32.f16 s7, s3
+; CHECK-NEXT: vcvtb.f32.f16 s10, s1
+; CHECK-NEXT: vcvtb.f32.f16 s6, s3
+; CHECK-NEXT: vcvtt.f32.f16 s9, s0
+; CHECK-NEXT: vcvtt.f32.f16 s5, s2
+; CHECK-NEXT: vcvtb.f32.f16 s8, s0
+; CHECK-NEXT: vcvtb.f32.f16 s4, s2
+; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%out = fpext <8 x half> %src1 to <8 x float>
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