[llvm] e461921 - [ARM] VPT validForTailPredication

[Sam Parker via llvm-commits]

Author: Sam Parker
Date: 2020-09-22T08:58:37+01:00
New Revision: e461921d6ccdd2a77209b2f4d3ca0a4db8e11c35

URL: https://github.com/llvm/llvm-project/commit/e461921d6ccdd2a77209b2f4d3ca0a4db8e11c35
DIFF: https://github.com/llvm/llvm-project/commit/e461921d6ccdd2a77209b2f4d3ca0a4db8e11c35.diff

LOG: [ARM] VPT validForTailPredication

Mark all VPT instructions as valid.

Differential Revision: https://reviews.llvm.org/D87759

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrMVE.td
    llvm/unittests/Target/ARM/MachineInstrTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 6c3d3be58c72..d9e9cf1176fc 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -6453,6 +6453,7 @@ class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> patte
   let Inst{4} = 0b0;
 
   let Defs = [VPR];
+  let validForTailPredication=1;
 }
 
 class MVE_VPTt1<string suffix, bits<2> size, dag iops>
@@ -6565,6 +6566,7 @@ class MVE_VPTf<string suffix, bit size, dag iops, string asm, list<dag> pattern=
 
   let Defs = [VPR];
   let Predicates = [HasMVEFloat];
+  let validForTailPredication=1;
 }
 
 class MVE_VPTft1<string suffix, bit size>

diff  --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
index 08cc81860a16..1ee6036a737b 100644
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -747,6 +747,28 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
     case MVE_VORRimmi16:
     case MVE_VORRimmi32:
     case MVE_VPST:
+    case MVE_VPTv16i8:
+    case MVE_VPTv8i16:
+    case MVE_VPTv4i32:
+    case MVE_VPTv16i8r:
+    case MVE_VPTv8i16r:
+    case MVE_VPTv4i32r:
+    case MVE_VPTv16s8:
+    case MVE_VPTv8s16:
+    case MVE_VPTv4s32:
+    case MVE_VPTv16s8r:
+    case MVE_VPTv8s16r:
+    case MVE_VPTv4s32r:
+    case MVE_VPTv16u8:
+    case MVE_VPTv8u16:
+    case MVE_VPTv4u32:
+    case MVE_VPTv16u8r:
+    case MVE_VPTv8u16r:
+    case MVE_VPTv4u32r:
+    case MVE_VPTv8f16:
+    case MVE_VPTv4f32:
+    case MVE_VPTv8f16r:
+    case MVE_VPTv4f32r:
     case MVE_VQABSs16:
     case MVE_VQABSs32:
     case MVE_VQABSs8: