[PATCH] D88072: [X86] Improve demanded bits for X86ISD::BEXTR.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 00:04:43 PDT 2020
craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.
craig.topper requested review of this revision.
If the control is constant we can figure out exactly which bits
of the input are demanded.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D88072
Files:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/tbm-intrinsics.ll
Index: llvm/test/CodeGen/X86/tbm-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/X86/tbm-intrinsics.ll
+++ llvm/test/CodeGen/X86/tbm-intrinsics.ll
@@ -61,3 +61,18 @@
%2 = select i1 %1, i32 %b, i32 %0
ret i32 %2
}
+
+define i32 @test_x86_tbm_bextri_demandedbits(i32 %x) nounwind readonly {
+; X86-LABEL: test_x86_tbm_bextri_demandedbits:
+; X86: # %bb.0:
+; X86-NEXT: bextrl $3841, {{[0-9]+}}(%esp), %eax # imm = 0xF01
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_tbm_bextri_demandedbits:
+; X64: # %bb.0:
+; X64-NEXT: bextrl $3841, %edi, %eax # imm = 0xF01
+; X64-NEXT: retq
+ %a = or i32 %x, 4294901761
+ %b = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a, i32 3841)
+ ret i32 %b
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38332,6 +38332,25 @@
Op, TLO.DAG.getNode(X86ISD::BEXTR, DL, VT, Op0,
TLO.DAG.getConstant(MaskedVal1, DL, VT)));
}
+
+ unsigned Shift = Cst1->getAPIntValue().extractBitsAsZExtValue(8, 0);
+ unsigned Length = Cst1->getAPIntValue().extractBitsAsZExtValue(8, 8);
+
+ // If the length is 0, the result is 0.
+ if (Length == 0) {
+ Known.setAllZero();
+ return false;
+ }
+
+ if ((Shift + Length) <= BitWidth) {
+ APInt DemandedMask = APInt::getBitsSet(BitWidth, Shift, Shift + Length);
+ if (SimplifyDemandedBits(Op0, DemandedMask, Known, TLO, Depth + 1))
+ return true;
+
+ Known = Known.extractBits(Length, Shift);
+ Known = Known.zextOrTrunc(BitWidth);
+ return false;
+ }
}
KnownBits Known1;
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