[PATCH] D88063: [SelectionDAG] Make sure FMF are propagated when getSetcc canonicalizes FP constants to RHS.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.
Herald added subscribers: ecnelises, hiraditya.
Herald added a project: LLVM.
craig.topper requested review of this revision.

getNode handling for ISD:SETCC calls FoldSETCC which can canonicalize
FP constants to the RHS. When this happens we should create the node
with the FMF that was requested.

There are probably other callers of FoldSETCC that need to be
updated, but this is one that was exposed by the recent changed to
create nodes with FMF in SelectionDAGBuilder instead of adding after
the fact.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88063

Files:
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/X86/fmf-propagation.ll


Index: llvm/test/CodeGen/X86/fmf-propagation.ll
===================================================================
--- llvm/test/CodeGen/X86/fmf-propagation.ll
+++ llvm/test/CodeGen/X86/fmf-propagation.ll
@@ -28,7 +28,7 @@
   ret float %f8
 }
 
-; CHECK: Optimized type-legalized selection DAG: %bb.0 'fmf_setcc:'
+; CHECK-LABEL: Optimized type-legalized selection DAG: %bb.0 'fmf_setcc:'
 ; CHECK: t13: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setlt:ch
 
 define float @fmf_setcc(float %x, float %y) {
@@ -36,3 +36,11 @@
   %ret = select i1 %cmp, float %x, float %y
   ret float %ret
 }
+
+; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_setcc_canon:'
+; CHECK: t14: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setgt:ch
+define float @fmf_setcc_canon(float %x, float %y) {
+  %cmp = fcmp fast ult float 0.0, %x
+  %ret = select i1 %cmp, float %x, float %y
+  ret float %ret
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2054,7 +2054,8 @@
 }
 
 SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
-                                ISD::CondCode Cond, const SDLoc &dl) {
+                                ISD::CondCode Cond, const SDLoc &dl,
+                                const SDNodeFlags Flags) {
   EVT OpVT = N1.getValueType();
 
   // These setcc operations always fold.
@@ -2184,7 +2185,7 @@
     ISD::CondCode SwappedCond = ISD::getSetCCSwappedOperands(Cond);
     if (!TLI->isCondCodeLegal(SwappedCond, OpVT.getSimpleVT()))
       return SDValue();
-    return getSetCC(dl, VT, N2, N1, SwappedCond);
+    return getSetCC(dl, VT, N2, N1, SwappedCond, Flags);
   } else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
              (OpVT.isFloatingPoint() && (N1.isUndef() || N2.isUndef()))) {
     // If an operand is known to be a nan (or undef that could be a nan), we can
@@ -5694,7 +5695,8 @@
                                   N1.getValueType().getVectorElementCount()) &&
            "SETCC vector element counts must match!");
     // Use FoldSetCC to simplify SETCC's.
-    if (SDValue V = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL))
+    if (SDValue V =
+            FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL, Flags))
       return V;
     // Vector constant folding.
     SDValue Ops[] = {N1, N2, N3};
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
===================================================================
--- llvm/include/llvm/CodeGen/SelectionDAG.h
+++ llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1646,9 +1646,10 @@
   SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT,
                              SDValue N1, SDValue N2);
 
-  /// Constant fold a setcc to true or false.
+  /// Constant fold a setcc to true or false or canonicalize floating point
+  /// constants to RHS.
   SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond,
-                    const SDLoc &dl);
+                    const SDLoc &dl, const SDNodeFlags Flags = SDNodeFlags());
 
   /// See if the specified operand can be simplified with the knowledge that
   /// only the bits specified by DemandedBits are used.  If so, return the


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