[llvm] bb82135 - [PowerPC] Remove unnecessary patterns and types

[Baptiste Saleil via llvm-commits]

Author: Baptiste Saleil
Date: 2020-09-21T16:08:54-05:00
New Revision: bb821355387fb4320322b8c2ff63994fffaf49ce

URL: https://github.com/llvm/llvm-project/commit/bb821355387fb4320322b8c2ff63994fffaf49ce
DIFF: https://github.com/llvm/llvm-project/commit/bb821355387fb4320322b8c2ff63994fffaf49ce.diff

LOG: [PowerPC] Remove unnecessary patterns and types

These patterns and type uses were added by mistake by commit
1372e23c7d4b25fd23689842246e66f70c949b46

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    llvm/lib/Target/PowerPC/PPCRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 00fd756fe46d..351f08dadadb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -747,7 +747,7 @@ let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
                                   IIC_LdStLFD, []>;
   def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src),
                               "lxvpx $XTp, $src", IIC_LdStLFD,
-                              [(set v4i64:$XTp, (load xaddr:$src))]>;
+                              []>;
   let Predicates = [PrefixInstrs] in {
     defm PLXVP :
       8LS_DForm_R_XTp5_SI34_MEM_p<1, 58, (outs vsrprc:$XTp), (ins memri34:$D_RA),
@@ -762,7 +762,7 @@ let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
                                    IIC_LdStLFD, []>;
   def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst),
                                "stxvpx $XTp, $dst", IIC_LdStLFD,
-                               [(store v4i64:$XTp, xaddr:$dst)]>;
+                               []>;
   let Predicates = [PrefixInstrs] in {
     defm PSTXVP :
       8LS_DForm_R_XTp5_SI34_MEM_p<1, 62, (outs), (ins vsrprc:$XTp, memri34:$D_RA),

diff  --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 3a5df2585ebc..850d7c6e42a8 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -399,7 +399,7 @@ def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
 
 // Allocate in the same order as the underlying VSX registers.
 def VSRpRC :
-  RegisterClass<"PPC", [v4i64,v4f64,v8i32,v8f32,v16i16,v32i8,v256i1], 128,
+  RegisterClass<"PPC", [v256i1], 128,
                 (add (sequence "VSRp%u", 0, 6),
                      (sequence "VSRp%u", 15, 7), VSRp17, VSRp18,
                      VSRp16, VSRp19, VSRp20, VSRp21, VSRp22, VSRp23,