[llvm] 6daddc2 - AMDGPU: Don't add frame register to frame pseudos

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-09-21T16:18:47-04:00
New Revision: 6daddc213fe56dccf1e88de61065c7fee09deccf

URL: https://github.com/llvm/llvm-project/commit/6daddc213fe56dccf1e88de61065c7fee09deccf
DIFF: https://github.com/llvm/llvm-project/commit/6daddc213fe56dccf1e88de61065c7fee09deccf.diff

LOG: AMDGPU: Don't add frame register to frame pseudos

We no longer treat the frame register like a function argument, so the
problem this avoided is no longer relevant.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index a91a652b8c14..73c65647352f 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4179,13 +4179,8 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
   case AMDGPU::ADJCALLSTACKDOWN: {
     const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
     MachineInstrBuilder MIB(*MF, &MI);
-
-    // Add an implicit use of the frame offset reg to prevent the restore copy
-    // inserted after the call from being reorderd after stack operations in the
-    // the caller's frame.
     MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
-        .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
-        .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
+       .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit);
     return BB;
   }
   case AMDGPU::SI_CALL_ISEL: {