[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.

The nits can be addressed when committing the code. LGTM otherwise.



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Comment at: llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1452
 // Vector Extend Sign
-def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;
-def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>;
-def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>;
-def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>;
-def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>;
+def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", [(set v4i32:$vD,
+                              (int_ppc_altivec_vextsb2w v16i8:$vB))]>;
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The indentation is off on all of these. Should probably be something like:
```
def VEXTSB2W :
  VX_VT5_EO5_VB5<1538, 16, "vextsb2w",
                 [(set v4i32:$vD, (int_ppc_altivec_vextsb2w v16i8:$vB))]>;
```


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Comment at: llvm/test/CodeGen/PowerPC/p10-vector-sign-extend.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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Nit: only one of these requires P10. The others are P9 instructions. You have split the tests for the front end changes, please split the back end test as well.


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https://reviews.llvm.org/D87394