[llvm] 29bd8ea - [ARM] Constant fold VMOVrh
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 20 13:33:06 PDT 2020
Author: David Green
Date: 2020-09-20T21:32:51+01:00
New Revision: 29bd8ea11091d996d166257e07bf2308651d284d
URL: https://github.com/llvm/llvm-project/commit/29bd8ea11091d996d166257e07bf2308651d284d
DIFF: https://github.com/llvm/llvm-project/commit/29bd8ea11091d996d166257e07bf2308651d284d.diff
LOG: [ARM] Constant fold VMOVrh
This adds simple constant folding for VMOVrh, to constant fold fp16
constants to integer values. It can help especially with soft calling
conventions, but some of the results are not optimal as we end up
loading using a vldr. This will be improved in a follow up patch.
Differential Revision: https://reviews.llvm.org/D87789
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
llvm/test/CodeGen/ARM/fp16-bitcast.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index d2e755b38ca9..0235d6aacfda 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13448,6 +13448,12 @@ static SDValue PerformVMOVrhCombine(SDNode *N,
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
+ // fold (VMOVrh (fpconst x)) -> const x
+ if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N0)) {
+ APFloat V = C->getValueAPF();
+ return DCI.DAG.getConstant(V.bitcastToAPInt().getZExtValue(), SDLoc(N), VT);
+ }
+
// fold (VMOVrh (load x)) -> (zextload (i16*)x)
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
diff --git a/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll b/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
index 444c689b6abb..d1272f88ede1 100644
--- a/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ b/llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -874,9 +874,7 @@ define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
; CHECK-MVE-NEXT: vstr fpcxtns, [sp, #-4]!
; CHECK-MVE-NEXT: push {r7, lr}
; CHECK-MVE-NEXT: sub sp, #4
-; CHECK-MVE-NEXT: vmov.f16 s0, #1.000000e+01
-; CHECK-MVE-NEXT: vmov.f16 r1, s0
-; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vldr s0, .LCPI11_0
; CHECK-MVE-NEXT: blx r0
; CHECK-MVE-NEXT: vmov.f16 r0, s0
; CHECK-MVE-NEXT: vmov s0, r0
@@ -886,6 +884,10 @@ define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
; CHECK-MVE-NEXT: vldr fpcxtns, [sp], #4
; CHECK-MVE-NEXT: clrm {r0, r1, r2, r3, r12, apsr}
; CHECK-MVE-NEXT: bxns lr
+; CHECK-MVE-NEXT: .p2align 2
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI11_0:
+; CHECK-MVE-NEXT: .long 0x00004900 @ float 2.61874657E-41
%call = call half %hptr(half 10.0) nounwind
ret half %call
}
@@ -929,43 +931,25 @@ define half @h2(half (half)* nocapture %hptr) nounwind {
; CHECK-8M-NEXT: .LCPI12_0:
; CHECK-8M-NEXT: .long 0x00004900 @ float 2.61874657E-41
;
-; CHECK-NO-MVE-LABEL: h2:
-; CHECK-NO-MVE: @ %bb.0: @ %entry
-; CHECK-NO-MVE-NEXT: push {r7, lr}
-; CHECK-NO-MVE-NEXT: vldr s0, .LCPI12_0
-; CHECK-NO-MVE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
-; CHECK-NO-MVE-NEXT: bic r0, r0, #1
-; CHECK-NO-MVE-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
-; CHECK-NO-MVE-NEXT: vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
-; CHECK-NO-MVE-NEXT: vstr fpcxts, [sp, #-8]!
-; CHECK-NO-MVE-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
-; CHECK-NO-MVE-NEXT: blxns r0
-; CHECK-NO-MVE-NEXT: vldr fpcxts, [sp], #8
-; CHECK-NO-MVE-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
-; CHECK-NO-MVE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
-; CHECK-NO-MVE-NEXT: pop {r7, pc}
-; CHECK-NO-MVE-NEXT: .p2align 2
-; CHECK-NO-MVE-NEXT: @ %bb.1:
-; CHECK-NO-MVE-NEXT: .LCPI12_0:
-; CHECK-NO-MVE-NEXT: .long 0x00004900 @ float 2.61874657E-41
-;
-; CHECK-MVE-LABEL: h2:
-; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: push {r7, lr}
-; CHECK-MVE-NEXT: vmov.f16 s0, #1.000000e+01
-; CHECK-MVE-NEXT: vmov.f16 r1, s0
-; CHECK-MVE-NEXT: vmov s0, r1
-; CHECK-MVE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
-; CHECK-MVE-NEXT: bic r0, r0, #1
-; CHECK-MVE-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
-; CHECK-MVE-NEXT: vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
-; CHECK-MVE-NEXT: vstr fpcxts, [sp, #-8]!
-; CHECK-MVE-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
-; CHECK-MVE-NEXT: blxns r0
-; CHECK-MVE-NEXT: vldr fpcxts, [sp], #8
-; CHECK-MVE-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
-; CHECK-MVE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
-; CHECK-MVE-NEXT: pop {r7, pc}
+; CHECK-81M-LABEL: h2:
+; CHECK-81M: @ %bb.0: @ %entry
+; CHECK-81M-NEXT: push {r7, lr}
+; CHECK-81M-NEXT: vldr s0, .LCPI12_0
+; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-81M-NEXT: bic r0, r0, #1
+; CHECK-81M-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+; CHECK-81M-NEXT: vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
+; CHECK-81M-NEXT: vstr fpcxts, [sp, #-8]!
+; CHECK-81M-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
+; CHECK-81M-NEXT: blxns r0
+; CHECK-81M-NEXT: vldr fpcxts, [sp], #8
+; CHECK-81M-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-81M-NEXT: pop {r7, pc}
+; CHECK-81M-NEXT: .p2align 2
+; CHECK-81M-NEXT: @ %bb.1:
+; CHECK-81M-NEXT: .LCPI12_0:
+; CHECK-81M-NEXT: .long 0x00004900 @ float 2.61874657E-41
entry:
%call = call half %hptr(half 10.0) "cmse_nonsecure_call" nounwind
ret half %call
@@ -1010,43 +994,25 @@ define half @h3(half (half)* nocapture %hptr) nounwind {
; CHECK-8M-NEXT: .LCPI13_0:
; CHECK-8M-NEXT: .long 0x00004900 @ float 2.61874657E-41
;
-; CHECK-NO-MVE-LABEL: h3:
-; CHECK-NO-MVE: @ %bb.0: @ %entry
-; CHECK-NO-MVE-NEXT: push {r7, lr}
-; CHECK-NO-MVE-NEXT: vldr s0, .LCPI13_0
-; CHECK-NO-MVE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
-; CHECK-NO-MVE-NEXT: bic r0, r0, #1
-; CHECK-NO-MVE-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
-; CHECK-NO-MVE-NEXT: vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
-; CHECK-NO-MVE-NEXT: vstr fpcxts, [sp, #-8]!
-; CHECK-NO-MVE-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
-; CHECK-NO-MVE-NEXT: blxns r0
-; CHECK-NO-MVE-NEXT: vldr fpcxts, [sp], #8
-; CHECK-NO-MVE-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
-; CHECK-NO-MVE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
-; CHECK-NO-MVE-NEXT: pop {r7, pc}
-; CHECK-NO-MVE-NEXT: .p2align 2
-; CHECK-NO-MVE-NEXT: @ %bb.1:
-; CHECK-NO-MVE-NEXT: .LCPI13_0:
-; CHECK-NO-MVE-NEXT: .long 0x00004900 @ float 2.61874657E-41
-;
-; CHECK-MVE-LABEL: h3:
-; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: push {r7, lr}
-; CHECK-MVE-NEXT: vmov.f16 s0, #1.000000e+01
-; CHECK-MVE-NEXT: vmov.f16 r1, s0
-; CHECK-MVE-NEXT: vmov s0, r1
-; CHECK-MVE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
-; CHECK-MVE-NEXT: bic r0, r0, #1
-; CHECK-MVE-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
-; CHECK-MVE-NEXT: vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
-; CHECK-MVE-NEXT: vstr fpcxts, [sp, #-8]!
-; CHECK-MVE-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
-; CHECK-MVE-NEXT: blxns r0
-; CHECK-MVE-NEXT: vldr fpcxts, [sp], #8
-; CHECK-MVE-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
-; CHECK-MVE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
-; CHECK-MVE-NEXT: pop {r7, pc}
+; CHECK-81M-LABEL: h3:
+; CHECK-81M: @ %bb.0: @ %entry
+; CHECK-81M-NEXT: push {r7, lr}
+; CHECK-81M-NEXT: vldr s0, .LCPI13_0
+; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-81M-NEXT: bic r0, r0, #1
+; CHECK-81M-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+; CHECK-81M-NEXT: vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
+; CHECK-81M-NEXT: vstr fpcxts, [sp, #-8]!
+; CHECK-81M-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
+; CHECK-81M-NEXT: blxns r0
+; CHECK-81M-NEXT: vldr fpcxts, [sp], #8
+; CHECK-81M-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-81M-NEXT: pop {r7, pc}
+; CHECK-81M-NEXT: .p2align 2
+; CHECK-81M-NEXT: @ %bb.1:
+; CHECK-81M-NEXT: .LCPI13_0:
+; CHECK-81M-NEXT: .long 0x00004900 @ float 2.61874657E-41
entry:
%call = tail call half %hptr(half 10.0) "cmse_nonsecure_call" nounwind
ret half %call
@@ -1157,9 +1123,7 @@ define half @h1_minsize(half (half)* nocapture %hptr) "cmse_nonsecure_entry" min
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vstr fpcxtns, [sp, #-4]!
; CHECK-MVE-NEXT: push {r6, r7, lr}
-; CHECK-MVE-NEXT: vmov.f16 s0, #1.000000e+01
-; CHECK-MVE-NEXT: vmov.f16 r1, s0
-; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vldr s0, .LCPI15_0
; CHECK-MVE-NEXT: blx r0
; CHECK-MVE-NEXT: vmov.f16 r0, s0
; CHECK-MVE-NEXT: vmov s0, r0
@@ -1168,6 +1132,10 @@ define half @h1_minsize(half (half)* nocapture %hptr) "cmse_nonsecure_entry" min
; CHECK-MVE-NEXT: vldr fpcxtns, [sp], #4
; CHECK-MVE-NEXT: clrm {r0, r1, r2, r3, r12, apsr}
; CHECK-MVE-NEXT: bxns lr
+; CHECK-MVE-NEXT: .p2align 2
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI15_0:
+; CHECK-MVE-NEXT: .long 0x00004900 @ float 2.61874657E-41
entry:
%call = call half %hptr(half 10.0) nounwind
ret half %call
diff --git a/llvm/test/CodeGen/ARM/fp16-bitcast.ll b/llvm/test/CodeGen/ARM/fp16-bitcast.ll
index 4d450e86d46f..ad3dc0a9efbf 100644
--- a/llvm/test/CodeGen/ARM/fp16-bitcast.ll
+++ b/llvm/test/CodeGen/ARM/fp16-bitcast.ll
@@ -138,8 +138,7 @@ define half @constcall() {
;
; CHECK-FP16-SOFT-LABEL: constcall:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
-; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, #1.000000e+01
-; CHECK-FP16-SOFT-NEXT: vmov.f16 r0, s0
+; CHECK-FP16-SOFT-NEXT: mov.w r0, #18688
; CHECK-FP16-SOFT-NEXT: b ccc
;
; CHECK-VFPV4-HARD-LABEL: constcall:
@@ -153,10 +152,12 @@ define half @constcall() {
;
; CHECK-FP16-HARD-LABEL: constcall:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
-; CHECK-FP16-HARD-NEXT: vmov.f16 s0, #1.000000e+01
-; CHECK-FP16-HARD-NEXT: vmov.f16 r0, s0
-; CHECK-FP16-HARD-NEXT: vmov s0, r0
+; CHECK-FP16-HARD-NEXT: vldr s0, .LCPI4_0
; CHECK-FP16-HARD-NEXT: b ccc
+; CHECK-FP16-HARD-NEXT: .p2align 2
+; CHECK-FP16-HARD-NEXT: @ %bb.1:
+; CHECK-FP16-HARD-NEXT: .LCPI4_0:
+; CHECK-FP16-HARD-NEXT: .long 0x00004900 @ float 2.61874657E-41
entry:
%call = tail call fast half @ccc(half 0xH4900)
ret half %call
More information about the llvm-commits
mailing list