[PATCH] D87847: [AMDGPU] global-isel support for RT

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:3044
+  auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opcode), DstReg);
+  if (Is64)
+    MIB.addReg(NodePtr, 0, AMDGPU::sub0)
----------------
Braces here


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:3059-3075
+  if (IsA16) {
+    MIB.addReg(RayDir, 0, AMDGPU::sub0);
+    Register R1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    Register R2 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    BuildMI(*MBB, &*MIB, DL, TII.get(AMDGPU::V_PACK_B32_F16), R1)
+      .addImm(0)
+      .addReg(RayDir, 0, AMDGPU::sub1)
----------------
Can you do this during custom lowering rather than adding bit operations here late? I'm also surprised a V_PACK_B32_F16 is involved here


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87847/new/

https://reviews.llvm.org/D87847