[PATCH] D84359: [PowerPC] Add vector pair load/store instructions and vector pair register class

[Baptiste Saleil via Phabricator via llvm-commits]

bsaleil updated this revision to Diff 292857.
bsaleil added a comment.

Remove unnecessary empty line and use the `printOperand` function to print `VSRp` regs


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84359/new/

https://reviews.llvm.org/D84359

Files:
  llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
  llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
  llvm/utils/TableGen/CodeGenTarget.cpp

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