[PATCH] D87879: [LoopInterchange] Add dominance check to guarantee output dependency order

[Mindong Chen via Phabricator via llvm-commits]

mdchen created this revision.
mdchen added reviewers: fhahn, efriedma.
mdchen added a project: LLVM.
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For a loop containing the following diamond structure:

     BB#1
    /    \
  BB#2   BB#3
    \    /
     BB#4

If the BranchInst condition in BB#1 relates to the loop induction
variable, and BB#3 and BB#4 both have stores writing to the same
memory location. Then these stores may have implicit loop-carried
order which could be broken after interchanging.

Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=47523


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87879

Files:
  llvm/lib/Transforms/Scalar/LoopInterchange.cpp
  llvm/test/Transforms/LoopInterchange/pr47523-implicit-out-dep-order.ll

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