[llvm] bea7749 - [AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 17 11:50:42 PDT 2020
Author: Amara Emerson
Date: 2020-09-17T11:50:32-07:00
New Revision: bea7749d0364a8c694f236a97d58167a33efdb9e
URL: https://github.com/llvm/llvm-project/commit/bea7749d0364a8c694f236a97d58167a33efdb9e
DIFF: https://github.com/llvm/llvm-project/commit/bea7749d0364a8c694f236a97d58167a33efdb9e.diff
LOG: [AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index f162f148f09d..cd470c9b7e9e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -14,6 +14,7 @@
#include "AArch64LegalizerInfo.h"
#include "AArch64Subtarget.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -97,15 +98,20 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0);
getActionDefinitionsBuilder(G_SHL)
- .legalFor({{s32, s32}, {s64, s64},
- {v2s32, v2s32}, {v4s32, v4s32}, {v2s64, v2s64}})
- .clampScalar(1, s32, s64)
- .clampScalar(0, s32, s64)
- .widenScalarToNextPow2(0)
- .clampNumElements(0, v2s32, v4s32)
- .clampNumElements(0, v2s64, v2s64)
- .moreElementsToNextPow2(0)
- .minScalarSameAs(1, 0);
+ .legalFor({{s32, s32},
+ {s64, s64},
+ {v2s32, v2s32},
+ {v4s32, v4s32},
+ {v2s64, v2s64},
+ {v16s8, v16s8},
+ {v8s16, v8s16}})
+ .clampScalar(1, s32, s64)
+ .clampScalar(0, s32, s64)
+ .widenScalarToNextPow2(0)
+ .clampNumElements(0, v2s32, v4s32)
+ .clampNumElements(0, v2s64, v2s64)
+ .moreElementsToNextPow2(0)
+ .minScalarSameAs(1, 0);
getActionDefinitionsBuilder(G_PTR_ADD)
.legalFor({{p0, s64}, {v2p0, v2s64}})
@@ -132,7 +138,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{s64, s64},
{v2s32, v2s32},
{v4s32, v4s32},
- {v2s64, v2s64}})
+ {v2s64, v2s64},
+ {v16s8, v16s8},
+ {v8s16, v8s16}})
.clampScalar(1, s32, s64)
.clampScalar(0, s32, s64)
.minScalarSameAs(1, 0);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
index 944ac8110ce0..05cb4cb2908a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
-# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
---
name: test_shift
body: |
@@ -284,3 +284,87 @@ body: |
RET_ReallyLR implicit $w0
...
+---
+name: test_ashr_v16i8
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_ashr_v16i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK: [[ASHR:%[0-9]+]]:_(<16 x s8>) = G_ASHR [[COPY]], [[COPY1]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ASHR]](<16 x s8>)
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = G_ASHR %0, %1
+ $q0 = COPY %2
+...
+---
+name: test_ashr_v8i16
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_ashr_v8i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+ ; CHECK: [[ASHR:%[0-9]+]]:_(<8 x s16>) = G_ASHR [[COPY]], [[COPY1]](<8 x s16>)
+ ; CHECK: $q0 = COPY [[ASHR]](<8 x s16>)
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(<8 x s16>) = COPY $q1
+ %2:_(<8 x s16>) = G_ASHR %0, %1
+ $q0 = COPY %2
+...
+---
+name: test_shl_v16i8
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_shl_v16i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[COPY]], [[COPY1]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[SHL]](<16 x s8>)
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = G_SHL %0, %1
+ $q0 = COPY %2
+...
+---
+name: test_shl_v8i16
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_shl_v8i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+ ; CHECK: [[SHL:%[0-9]+]]:_(<8 x s16>) = G_SHL [[COPY]], [[COPY1]](<8 x s16>)
+ ; CHECK: $q0 = COPY [[SHL]](<8 x s16>)
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(<8 x s16>) = COPY $q1
+ %2:_(<8 x s16>) = G_SHL %0, %1
+ $q0 = COPY %2
+...
+---
+name: test_lshr_v16i8
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_lshr_v16i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK: [[LSHR:%[0-9]+]]:_(<16 x s8>) = G_LSHR [[COPY]], [[COPY1]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[LSHR]](<16 x s8>)
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = G_LSHR %0, %1
+ $q0 = COPY %2
+...
+---
+name: test_lshr_v8i16
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_lshr_v8i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+ ; CHECK: [[LSHR:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[COPY]], [[COPY1]](<8 x s16>)
+ ; CHECK: $q0 = COPY [[LSHR]](<8 x s16>)
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(<8 x s16>) = COPY $q1
+ %2:_(<8 x s16>) = G_LSHR %0, %1
+ $q0 = COPY %2
+...
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