[PATCH] D87843: [SVE] Change definition of reduction ISD nodes to have an SVE vector result type.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.
paulwalker-arm requested review of this revision.

The current nodes, AArch64::SMAXV_PRED for example, are defined to
return a NEON vector result.  This is incorrect because they modify
the complete SVE register and are thus changed to represent such.

This patch also adds nodes for UADDV_PRED and SADDV_PRED, which
unifies the handling of all SVE reductions.

NOTE: Floating-point reductions are already implemented correctly,
so this patch is essentially making everything consistent with those.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87843

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td

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