[PATCH] D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Oh, I hadn't realised we are handling reduction in this way upstream (although it does match an old design we had downstream).  This is certainly not the expected behaviour so I'll get it fixed.  The expectation is for the SVE reduction ISD nodes to reflect the underlying instructions behaviour, which is they set the whole vector register.  The reason for this is that we don't want the element extraction to be done during isel because it introduces needless vpr-gpr transitions and there are also use cases that make use of the implicit zeroing of the upper lanes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87796/new/

https://reviews.llvm.org/D87796