[PATCH] D87502: [DAGCombiner] Use known bits to fold extract_vector_elt with const index

[Jay Foad via Phabricator via llvm-commits]

foad added a subscriber: t.p.northover.
foad added a comment.

In D87502#2267572 <https://reviews.llvm.org/D87502#2267572>, @foad wrote:

> This isn't ready to commit yet:
>
> 1. there are a few code quality regressions in the test cases
> 2. it provokes a crash on `test/CodeGen/AMDGPU/global-extload-i16.ll` which I haven't been able to fix yet

Update:

1. See inline comments on the regressions.
2. The crash is fixed. See D87757 <https://reviews.llvm.org/D87757>.



================
Comment at: llvm/test/CodeGen/Mips/cconv/vector.ll:4206-4247
+; MIPS64R5EB-LABEL: calli8_16:
+; MIPS64R5EB:       # %bb.0: # %entry
+; MIPS64R5EB-NEXT:    daddiu $sp, $sp, -16
+; MIPS64R5EB-NEXT:    .cfi_def_cfa_offset 16
+; MIPS64R5EB-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPS64R5EB-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
+; MIPS64R5EB-NEXT:    .cfi_offset 31, -8
----------------
There are some regressions in this file but also some improvements. I haven't worked out what's going on yet.


================
Comment at: llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll:218-231
 ; CHECK-NEXT:    vand q0, q0, q2
-; CHECK-NEXT:    vmov r0, s4
+; CHECK-NEXT:    vand q1, q1, q2
+; CHECK-NEXT:    vmov r0, s6
+; CHECK-NEXT:    vmov r1, s2
+; CHECK-NEXT:    vmov r2, s0
+; CHECK-NEXT:    muls r0, r1, r0
+; CHECK-NEXT:    vmov r1, s4
----------------
Regression here and in other cases that are now using muls instead of umull/umlal.


================
Comment at: llvm/test/CodeGen/X86/vector-fshl-128.ll:188-189
 ; X32-SSE-NEXT:    psrlq %xmm4, %xmm5
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
+; X32-SSE-NEXT:    pxor %xmm6, %xmm6
+; X32-SSE-NEXT:    punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm6[2],xmm4[3],xmm6[3]
 ; X32-SSE-NEXT:    psrlq %xmm4, %xmm1
----------------
Regression. Quite a few tests are now using pxor+punpckhdq instead of pshufd. I wonder if some kind of combine could spot this case and turn it back into pshufd.


================
Comment at: llvm/test/CodeGen/X86/vector-trunc-math.ll:2713
 ; SSE-NEXT:    packuswb %xmm1, %xmm0
+; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
 ; SSE-NEXT:    retq
----------------
Regression. Perhaps we need better known bits analysis.


Repository:
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