[PATCH] D87771: [AArch64] Emit zext move when the source of the zext is AssertZext or AssertSext

[weiwei via Phabricator via llvm-commits]

wwei created this revision.
wwei added reviewers: t.p.northover, paulwalker-arm, efriedma, dmgreen, samparker.
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Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
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When the source of the zext is AssertZext or AssertSext, it is hard to know any information about the upper 32 bits,
so we should insert a zext move before emitting SUBREG_TO_REG to define the lower 32 bits.

Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=47543


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87771

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/arm64-assert-zext-sext.ll
  llvm/test/CodeGen/AArch64/shift_minsize.ll

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