[PATCH] D87231: [AArch64] Match pairwise fadd pattern

[Sanne Wouda via Phabricator via llvm-commits]

sanwou01 added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11598
+  if (ConstantN1 && ConstantN1->getZExtValue() == 0 &&
+      N0->getOpcode() == ISD::FADD && VT == MVT::f32) {
+    SDLoc DL(N0);
----------------
dmgreen wrote:
> Could this apply equally for f16/f64 as well?
I think so. Looks like we're missing the f16 FADDP pattern in ISel so might as well add that too.

Similar for i64 ADDP actually.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87231/new/

https://reviews.llvm.org/D87231