[PATCH] D87231: [AArch64] ExtractElement is free when combined with pairwise add

[Sanne Wouda via Phabricator via llvm-commits]

sanwou01 added a comment.

Thanks for the feedback. I agree that ideally we'd be generating reduction intrinsics in IR and matching that in the backends. I don't think the pairwise add can be represented with the current intrinsics though: we'd need a `<2 x float>` variant, or a predicated version of the `<4 x float>` intrinsic to do this for strict FP math, I believe.

So at least for the moment I'll continue playing whack-a-mole and match the pattern in AArch64 ISel lowering.


Repository:
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  https://reviews.llvm.org/D87231/new/

https://reviews.llvm.org/D87231