[llvm] 2ce1a69 - [X86] Always use 16-bit displacement in 16-bit mode when there is no base or index register.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-09-15T19:31:48-07:00
New Revision: 2ce1a697f037469e737db1ad41dfa14ec653ec53

URL: https://github.com/llvm/llvm-project/commit/2ce1a697f037469e737db1ad41dfa14ec653ec53
DIFF: https://github.com/llvm/llvm-project/commit/2ce1a697f037469e737db1ad41dfa14ec653ec53.diff

LOG: [X86] Always use 16-bit displacement in 16-bit mode when there is no base or index register.

Previously we only did this if the immediate fit in 16 bits, but
the GNU assembler seems to just truncate.

Fixes PR46952

Added: 
    

Modified: 
    llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
    llvm/test/MC/X86/x86-16.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 0de94cda2d73..533145e57ca5 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -161,13 +161,11 @@ static bool is16BitMemOperand(const MCInst &MI, unsigned Op,
                               const MCSubtargetInfo &STI) {
   const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
   const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);
-  const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
 
   unsigned BaseReg = Base.getReg();
   unsigned IndexReg = Index.getReg();
 
-  if (STI.hasFeature(X86::Mode16Bit) && BaseReg == 0 && IndexReg == 0 &&
-      Disp.isImm() && Disp.getImm() < 0x10000)
+  if (STI.hasFeature(X86::Mode16Bit) && BaseReg == 0 && IndexReg == 0)
     return true;
   if ((BaseReg != 0 &&
        X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) ||

diff  --git a/llvm/test/MC/X86/x86-16.s b/llvm/test/MC/X86/x86-16.s
index f92164e57314..f1b4428703f1 100644
--- a/llvm/test/MC/X86/x86-16.s
+++ b/llvm/test/MC/X86/x86-16.s
@@ -1056,3 +1056,8 @@ foo:
 // CHECK:  encoding: [0x0f,0x84,A,A]
 // CHECK:  fixup A - offset: 2, value: foo-2, kind: FK_PCRel_2
 {disp32} je foo
+
+// CHECK: movl nearer, %ebx
+// CHECK:  encoding: [0x66,0x8b,0x1e,A,A]
+// CHECK:  fixup A - offset: 3, value: nearer, kind: FK_Data_2
+movl    nearer, %ebx