[PATCH] D87618: [AMDGPU] should expand ROTL i16 to shifts.

[Alexander via Phabricator via llvm-commits]

alex-t updated this revision to Diff 291967.
alex-t added a comment.

Tests added. ROTR case added.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87618/new/

https://reviews.llvm.org/D87618

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/shift-rotate.ll


Index: llvm/test/CodeGen/AMDGPU/shift-rotate.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/shift-rotate.ll
@@ -0,0 +1,53 @@
+; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=gfx1010 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: @test_rotl
+; GCN: global_load_ushort [[X:v[0-9]+]]
+; GCN: global_load_ushort [[D:v[0-9]+]]
+; GCN: v_sub_nc_u16_e64 [[NX:v[0-9]+]], 0, [[X]]
+; GCN: v_and_b32_e32 [[XAND:v[0-9]+]], 15, [[X]]
+; GCN: v_and_b32_e32 [[NXAND:v[0-9]+]], 15, [[NX]]
+; GCN: v_lshlrev_b16_e64 [[LO:v[0-9]+]], [[XAND]], [[D]]
+; GCN: v_lshrrev_b16_e64 [[HI:v[0-9]+]], [[NXAND]], [[D]]
+; GCN: v_or_b32_e32 [[RES:v[0-9]+]], [[LO]], [[HI]]
+; GCN: global_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RES]]
+
+  declare i16 @llvm.fshl.i16(i16, i16, i16)
+
+  define void @test_rotl(i16 addrspace(1)* nocapture readonly %sourceA, i16 addrspace(1)* nocapture readonly %sourceB, i16 addrspace(1)* nocapture %destValues) {
+  entry:
+    %arrayidx = getelementptr inbounds i16, i16 addrspace(1)* %sourceA, i64 16
+    %a = load i16, i16 addrspace(1)* %arrayidx
+    %arrayidx2 = getelementptr inbounds i16, i16 addrspace(1)* %sourceB, i64 24
+    %b = load i16, i16 addrspace(1)* %arrayidx2
+    %c = tail call i16 @llvm.fshl.i16(i16 %a, i16 %a, i16 %b)
+    %arrayidx5 = getelementptr inbounds i16, i16 addrspace(1)* %destValues, i64 4
+    store i16 %c, i16 addrspace(1)* %arrayidx5
+    ret void
+  }
+
+
+; GCN-LABEL: @test_rotr
+; GCN: global_load_ushort [[X:v[0-9]+]]
+; GCN: global_load_ushort [[D:v[0-9]+]]
+; GCN: v_sub_nc_u16_e64 [[NX:v[0-9]+]], 0, [[X]]
+; GCN: v_and_b32_e32 [[XAND:v[0-9]+]], 15, [[X]]
+; GCN: v_and_b32_e32 [[NXAND:v[0-9]+]], 15, [[NX]]
+; GCN: v_lshrrev_b16_e64 [[LO:v[0-9]+]], [[XAND]], [[D]]
+; GCN: v_lshlrev_b16_e64 [[HI:v[0-9]+]], [[NXAND]], [[D]]
+; GCN: v_or_b32_e32 [[RES:v[0-9]+]], [[LO]], [[HI]]
+; GCN: global_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RES]]
+
+  declare i16 @llvm.fshr.i16(i16, i16, i16)
+
+  define void @test_rotr(i16 addrspace(1)* nocapture readonly %sourceA, i16 addrspace(1)* nocapture readonly %sourceB, i16 addrspace(1)* nocapture %destValues) {
+  entry:
+    %arrayidx = getelementptr inbounds i16, i16 addrspace(1)* %sourceA, i64 16
+    %a = load i16, i16 addrspace(1)* %arrayidx
+    %arrayidx2 = getelementptr inbounds i16, i16 addrspace(1)* %sourceB, i64 24
+    %b = load i16, i16 addrspace(1)* %arrayidx2
+    %c = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %b)
+    %arrayidx5 = getelementptr inbounds i16, i16 addrspace(1)* %destValues, i64 4
+    store i16 %c, i16 addrspace(1)* %arrayidx5
+    ret void
+  }
+
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -545,8 +545,8 @@
     setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
     AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
 
-    setOperationAction(ISD::ROTR, MVT::i16, Promote);
-    setOperationAction(ISD::ROTL, MVT::i16, Promote);
+    setOperationAction(ISD::ROTR, MVT::i16, Expand);
+    setOperationAction(ISD::ROTL, MVT::i16, Expand);
 
     setOperationAction(ISD::SDIV, MVT::i16, Promote);
     setOperationAction(ISD::UDIV, MVT::i16, Promote);


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