[llvm] 6352381 - [Hexagon] Some HVX DAG combines

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2020-09-14T18:10:23-05:00
New Revision: 6352381039c43c66f01a23be19472f7e611ffcdf

URL: https://github.com/llvm/llvm-project/commit/6352381039c43c66f01a23be19472f7e611ffcdf
DIFF: https://github.com/llvm/llvm-project/commit/6352381039c43c66f01a23be19472f7e611ffcdf.diff

LOG: [Hexagon] Some HVX DAG combines

1. VINSERTW0 x, undef -> x
2. VROR (VROR x, a), b) -> VROR x, a+b

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 65bc2e3577cc..51804e5f5327 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -2112,22 +2112,40 @@ HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
       const {
   if (DCI.isBeforeLegalizeOps())
     return SDValue();
+
   const SDLoc &dl(N);
+  SelectionDAG &DAG = DCI.DAG;
   SDValue Op(N, 0);
 
   unsigned Opc = Op.getOpcode();
-  if (Opc == ISD::VSELECT) {
-    // (vselect (xor x, qtrue), v0, v1) -> (vselect x, v1, v0)
-    SDValue Cond = Op.getOperand(0);
-    if (Cond->getOpcode() == ISD::XOR) {
-      SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
-      if (C1->getOpcode() == HexagonISD::QTRUE) {
-        SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
-                                       Op.getOperand(2), Op.getOperand(1));
-        return VSel;
+  switch (Opc) {
+    case ISD::VSELECT: {
+      // (vselect (xor x, qtrue), v0, v1) -> (vselect x, v1, v0)
+      SDValue Cond = Op.getOperand(0);
+      if (Cond->getOpcode() == ISD::XOR) {
+        SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
+        if (C1->getOpcode() == HexagonISD::QTRUE)
+          return DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
+                             Op.getOperand(2), Op.getOperand(1));
+      }
+      break;
+    }
+    case HexagonISD::VINSERTW0:
+      if (isUndef(Op.getOperand(1)))
+        return Op.getOperand(0);
+      break;
+    case HexagonISD::VROR: {
+      SDValue Op0 = Op.getOperand(0);
+      if (Op0.getOpcode() == HexagonISD::VROR) {
+        SDValue Vec = Op0.getOperand(0);
+        SDValue Rot0 = Op.getOperand(1), Rot1 = Op0.getOperand(1);
+        SDValue Rot = DAG.getNode(ISD::ADD, dl, ty(Rot0), {Rot0, Rot1});
+        return DAG.getNode(HexagonISD::VROR, dl, ty(Op), {Vec, Rot});
       }
+      break;
     }
   }
+
   return SDValue();
 }