[PATCH] D87538: [VectorCombine] Don't vectorize scalar load under asan/hwasan/memtag/tsan

[Vitaly Buka via Phabricator via llvm-commits]

vitalybuka accepted this revision.
vitalybuka added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Analysis/ValueTracking.cpp:4414
 bool llvm::mustSuppressSpeculation(const LoadInst &LI) {
-  if (!LI.isUnordered())
+  if (!LI.isSimple())
     return true;
----------------
MaskRay wrote:
> spatel wrote:
> > Definitely get a 2nd reviewer opinion if we are making changes here (I don't know enough about this)...
> > But if I'm seeing it correctly, isSimple() is not a superset of isUnordered(). Ie, a load can have AtomicOrdering::Unordered but still be simple?
> isSimple is a subset of isUnordered. An AtomicOrdering::Unordered load is `isUnordered` but not `isSimple`.
Should this be a separate patch?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87538/new/

https://reviews.llvm.org/D87538