[llvm] f859c30 - [AMDGPU] Add XDL resource to scheduling model

[Austin Kerbow via llvm-commits]

Author: Austin Kerbow
Date: 2020-09-14T13:48:54-07:00
New Revision: f859c30ecbbbeb33a90b00b76044a688b2e71879

URL: https://github.com/llvm/llvm-project/commit/f859c30ecbbbeb33a90b00b76044a688b2e71879
DIFF: https://github.com/llvm/llvm-project/commit/f859c30ecbbbeb33a90b00b76044a688b2e71879.diff

LOG: [AMDGPU] Add XDL resource to scheduling model

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D87621

Added: 
    llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll

Modified: 
    llvm/lib/Target/AMDGPU/SISchedule.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td
index 932381c99e0b..d6dff4b9c889 100644
--- a/llvm/lib/Target/AMDGPU/SISchedule.td
+++ b/llvm/lib/Target/AMDGPU/SISchedule.td
@@ -104,6 +104,9 @@ def HWVALU   : ProcResource<1> {
 def HWRC   : ProcResource<1> { // Register destination cache
   let BufferSize = 1;
 }
+def HWXDL   : ProcResource<1> { // MFMA CU
+  let BufferSize = 0;
+}
 
 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
                  int latency> : WriteRes<write, resources> {
@@ -138,9 +141,13 @@ multiclass SICommonWriteRes {
   def : HWVALUWriteRes<WriteFloatCvt,      4>;
   def : HWVALUWriteRes<WriteTrans32,       4>;
   def : HWVALUWriteRes<WriteQuarterRate32, 4>;
-  def : HWVALUWriteRes<Write2PassMAI,      2>;
-  def : HWVALUWriteRes<Write8PassMAI,      8>;
-  def : HWVALUWriteRes<Write16PassMAI,    16>;
+
+  let ResourceCycles = [2] in
+  def : HWWriteRes<Write2PassMAI,  [HWXDL], 2>;
+  let ResourceCycles = [8] in
+  def : HWWriteRes<Write8PassMAI,  [HWXDL], 8>;
+  let ResourceCycles = [16] in
+  def : HWWriteRes<Write16PassMAI, [HWXDL], 16>;
 
   def : ReadAdvance<MIVGPRRead, -2>;
   def : InstRW<[Write64Bit, MIReadVGPR], (instregex "^V_ACCVGPR_WRITE_B32$")>;

diff  --git a/llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll b/llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
new file mode 100644
index 000000000000..6beddf8fe947
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
@@ -0,0 +1,44 @@
+; RUN: llc -march=amdgcn -mcpu=gfx908 -debug-only=machine-scheduler -verify-machineinstrs < %s 2>&1 | FileCheck -enable-var-scope %s
+; REQUIRES: asserts
+
+declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half>, <4 x half>, <32 x float>, i32, i32, i32)
+
+; CHECK: CritRes: {{[0-9]+}} HWXDL
+; CHECK: Picking: Cand SU([[nid:[0-9]+]]) RES-DEMAND
+; CHECK: Scheduling SU([[nid]]) {{.*}} V_MFMA_F32_32X32X4F16
+define amdgpu_kernel void @schedule-xdl-resource(<32 x float> addrspace(1)* %in, <32 x float> addrspace(1)* %out, <4 x half> addrspace(3)* %lds, i32 %stride) #0 {
+  %in_ptr.1 = getelementptr <32 x float>, <32 x float> addrspace(1)* %in, i32 %stride
+  %in_ptr.2 = getelementptr <32 x float>, <32 x float> addrspace(1)* %in_ptr.1, i32 %stride
+  %in_ptr.3 = getelementptr <32 x float>, <32 x float> addrspace(1)* %in_ptr.2, i32 %stride
+  %in.load.1 = load <32 x float>, <32 x float> addrspace (1)* %in_ptr.1
+  %in.load.2 = load <32 x float>, <32 x float> addrspace (1)* %in_ptr.2
+  %in.load.3 = load <32 x float>, <32 x float> addrspace (1)* %in_ptr.3
+  %lds_ptr.1 = getelementptr <4 x half>, <4 x half> addrspace(3)* %lds, i32 %stride
+  %lds_ptr.2 = getelementptr <4 x half>, <4 x half> addrspace(3)* %lds_ptr.1, i32 %stride
+  %lds_ptr.3 = getelementptr <4 x half>, <4 x half> addrspace(3)* %lds_ptr.2, i32 %stride
+  %lds.load.1 = load <4 x half>, <4 x half> addrspace(3)* %lds_ptr.1
+  %lds.load.2 = load <4 x half>, <4 x half> addrspace(3)* %lds_ptr.2
+  %lds.load.3 = load <4 x half>, <4 x half> addrspace(3)* %lds_ptr.3
+  %mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.1, <4 x half> %lds.load.1, <32 x float> %in.load.1, i32 1, i32 1, i32 1)
+  %mai.2 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.2, <4 x half> %lds.load.2, <32 x float> %in.load.2, i32 1, i32 1, i32 1)
+  %mai.3 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.3, <4 x half> %lds.load.3, <32 x float> %in.load.3, i32 1, i32 1, i32 1)
+  %mai.4 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.1, <4 x half> %lds.load.1, <32 x float> %in.load.1, i32 2, i32 2, i32 2)
+  %mai.5 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.2, <4 x half> %lds.load.2, <32 x float> %in.load.2, i32 2, i32 2, i32 2)
+  %mai.6 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.3, <4 x half> %lds.load.3, <32 x float> %in.load.3, i32 2, i32 2, i32 2)
+  %out_ptr.1 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out, i32 %stride
+  %out_ptr.2 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.1, i32 %stride
+  %out_ptr.3 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.2, i32 %stride
+  %out_ptr.4 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.3, i32 %stride
+  %out_ptr.5 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.4, i32 %stride
+  %out_ptr.6 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.5, i32 %stride
+  store <32 x float> %mai.1, <32 x float> addrspace(1)* %out_ptr.1
+  store <32 x float> %mai.2, <32 x float> addrspace(1)* %out_ptr.2
+  store <32 x float> %mai.3, <32 x float> addrspace(1)* %out_ptr.3
+  store <32 x float> %mai.4, <32 x float> addrspace(1)* %out_ptr.4
+  store <32 x float> %mai.5, <32 x float> addrspace(1)* %out_ptr.5
+  store <32 x float> %mai.6, <32 x float> addrspace(1)* %out_ptr.6
+
+  ret void
+}
+
+attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" }