[PATCH] D52010: RegAllocFast: Rewrite and improve

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 14 11:07:17 PDT 2020 

arsenm updated this revision to Diff 291622.
arsenm added a comment.

Fix verifier error from live out eflags encountered when looking at the testcase from bug 47278. There was an if 0'd out section for dealing with live-ins. Add all live out registers as pre-assigned. Previously allocatable live out physregs would be incorrectly killed, and non-allocatable registers would hit a verifier error


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D52010/new/

https://reviews.llvm.org/D52010

Files:
  llvm/lib/CodeGen/RegAllocFast.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll
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  llvm/test/CodeGen/AArch64/cmpxchg-O0.ll
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  llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
  llvm/test/CodeGen/AArch64/popcount.ll
  llvm/test/CodeGen/AArch64/swift-return.ll
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  llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
  llvm/test/CodeGen/AArch64/unwind-preserved.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
  llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
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  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
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  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
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  llvm/test/CodeGen/Mips/msa/ldr_str.ll
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  llvm/test/CodeGen/SPARC/fp16-promote.ll
  llvm/test/CodeGen/SystemZ/swift-return.ll
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  llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
  llvm/test/CodeGen/Thumb2/high-reg-spill.mir
  llvm/test/CodeGen/Thumb2/mve-vector-spill.ll
  llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
  llvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
  llvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
  llvm/test/CodeGen/X86/atomic-monotonic.ll
  llvm/test/CodeGen/X86/atomic-unordered.ll
  llvm/test/CodeGen/X86/atomic32.ll
  llvm/test/CodeGen/X86/atomic64.ll
  llvm/test/CodeGen/X86/atomic6432.ll
  llvm/test/CodeGen/X86/avx-load-store.ll
  llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
  llvm/test/CodeGen/X86/bug47278-eflags-error.mir
  llvm/test/CodeGen/X86/crash-O0.ll
  llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll
  llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
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  llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
  llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
  llvm/test/CodeGen/X86/phys-reg-local-regalloc.ll
  llvm/test/CodeGen/X86/pr11415.ll
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  llvm/test/CodeGen/X86/pr44749.ll
  llvm/test/CodeGen/X86/pr47000.ll
  llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
  llvm/test/CodeGen/X86/stack-protector-msvc.ll
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  llvm/test/CodeGen/X86/swift-return.ll
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  llvm/test/CodeGen/X86/win64_eh.ll
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  llvm/test/DebugInfo/AArch64/frameindices.ll
  llvm/test/DebugInfo/AArch64/prologue_end.ll
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  llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll
  llvm/test/DebugInfo/X86/sret.ll
  llvm/test/DebugInfo/X86/subreg.ll

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