[llvm] 00e5676 - [LegalizeDAG] Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-09-14T11:09:43+01:00
New Revision: 00e5676cf64740daf99b694d1ac968be141b655f

URL: https://github.com/llvm/llvm-project/commit/00e5676cf64740daf99b694d1ac968be141b655f
DIFF: https://github.com/llvm/llvm-project/commit/00e5676cf64740daf99b694d1ac968be141b655f.diff

LOG: [LegalizeDAG] Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 71ba228b53f6..541edafc0ef5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2800,7 +2800,7 @@ SDValue SelectionDAGLegalize::ExpandPARITY(SDValue Op, const SDLoc &dl) {
     Result = Op;
     for (unsigned i = Log2_32_Ceil(Sz); i != 0;) {
       SDValue Shift = DAG.getNode(ISD::SRL, dl, VT, Result,
-                                  DAG.getConstant(1 << (--i), dl, ShVT));
+                                  DAG.getConstant(1ULL << (--i), dl, ShVT));
       Result = DAG.getNode(ISD::XOR, dl, VT, Result, Shift);
     }
   }