[PATCH] D87569: [LegalizeFloatType][ARM] Add float legalization for VECREDUCE

Nikita Popov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Sep 12 13:54:12 PDT 2020


nikic created this revision.
nikic added reviewers: dmgreen, spatel, RKSimon.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
nikic requested review of this revision.

This adds SoftenFloatRes and PromoteFloatRes legalizations for VECREDUCE, to fill the remaining hole in the SDAG legalization. These legalizations simplify expand the reduction and let it be recursively legalized. For the PromoteFloatRes case it is possible to do better than that, but it's pretty tricky (because we need to consider the interaction of three different vector legalizations and the type promotion) and probably not really worthwhile.

I haven't added SoftPromoteHalfRes or ExpandFloatRes support, as the targets for which these are relevant (X86 and PPC respectively) do not use VECREDUCE legalization, so there's no good way to test them.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87569

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll

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