[llvm] 93b4f85 - Update TableGen test files to use the new '...' range punctuation.
Paul C. Anagnostopoulos via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 12 13:28:34 PDT 2020
Author: Paul C. Anagnostopoulos
Date: 2020-09-12T16:26:32-04:00
New Revision: 93b4f8538267e620de4a36e7cf0abc0d4f8d7c10
URL: https://github.com/llvm/llvm-project/commit/93b4f8538267e620de4a36e7cf0abc0d4f8d7c10
DIFF: https://github.com/llvm/llvm-project/commit/93b4f8538267e620de4a36e7cf0abc0d4f8d7c10.diff
LOG: Update TableGen test files to use the new '...' range punctuation.
Added:
Modified:
llvm/test/TableGen/BitsInit.td
llvm/test/TableGen/DAGDefaultOps.td
llvm/test/TableGen/ForeachLoop.td
llvm/test/TableGen/HwModeEncodeDecode.td
llvm/test/TableGen/JSON.td
llvm/test/TableGen/ListSlices.td
llvm/test/TableGen/UnsetBitInit.td
llvm/test/TableGen/cond-let.td
llvm/test/TableGen/dag-isel-regclass-emit-enum.td
llvm/test/TableGen/defset.td
llvm/test/TableGen/foreach-variable-range.td
llvm/test/TableGen/if.td
llvm/test/TableGen/ifstmt.td
llvm/test/TableGen/list-element-bitref.td
llvm/test/TableGen/range-lists.td
llvm/test/TableGen/simplify-patfrag.td
llvm/test/TableGen/trydecode-emission3.td
Removed:
################################################################################
diff --git a/llvm/test/TableGen/BitsInit.td b/llvm/test/TableGen/BitsInit.td
index 6f9acd346ba8..c5527aebb941 100644
--- a/llvm/test/TableGen/BitsInit.td
+++ b/llvm/test/TableGen/BitsInit.td
@@ -38,8 +38,8 @@ def {
bits<2> D8 = { 0 }; // type mismatch. RHS doesn't have enough bits
bits<8> E;
- let E{7..0} = {0,0,1,?,?,?,?,?};
- let E{3-0} = 0b0010;
+ let E{7...0} = {0,0,1,?,?,?,?,?};
+ let E{3...0} = 0b0010;
bits<8> F1 = { 0, 1, 0b1001, 0, 0b0 }; // ok
bits<7> F2 = { 0, 1, 0b1001, 0, 0b0 }; // LHS doesn't have enough bits
@@ -50,7 +50,7 @@ def {
bits<8> G3 = { 0, 1, { 0b1001 }, 0, 0b0 }; // ok
bits<16> H;
- let H{15-0} = { { 0b11001100 }, 0b00110011 };
+ let H{15...0} = { { 0b11001100 }, 0b00110011 };
bits<16> I = { G1, G2 };
// Make sure we can initialise ints with bits<> values.
diff --git a/llvm/test/TableGen/DAGDefaultOps.td b/llvm/test/TableGen/DAGDefaultOps.td
index 1c98c4d8d07b..702a2232db30 100644
--- a/llvm/test/TableGen/DAGDefaultOps.td
+++ b/llvm/test/TableGen/DAGDefaultOps.td
@@ -16,10 +16,10 @@ class TestEncoding : Instruction {
}
class TestReg<int index> : Register<"R"#index, []> {
- let HWEncoding{15-4} = 0;
- let HWEncoding{3-0} = !cast<bits<4>>(index);
+ let HWEncoding{15...4} = 0;
+ let HWEncoding{3...0} = !cast<bits<4>>(index);
}
-foreach i = 0-15 in
+foreach i = 0...15 in
def "R"#i : TestReg<i>;
def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 15)>;
@@ -36,11 +36,11 @@ class RRI<string Mnemonic, bits<4> Opcode> : TestEncoding {
field bits<4> src1;
field bits<4> src2;
field bits<16> imm;
- let Inst{31-28} = Opcode;
- let Inst{27-24} = dest;
- let Inst{23-20} = src1;
- let Inst{19-16} = src2;
- let Inst{15-0} = imm;
+ let Inst{31...28} = Opcode;
+ let Inst{27...24} = dest;
+ let Inst{23...20} = src1;
+ let Inst{19...16} = src2;
+ let Inst{15...0} = imm;
}
def AddRRI : RRI<"add", 0b0001>;
diff --git a/llvm/test/TableGen/ForeachLoop.td b/llvm/test/TableGen/ForeachLoop.td
index ce8d44c7526e..173285b5e722 100644
--- a/llvm/test/TableGen/ForeachLoop.td
+++ b/llvm/test/TableGen/ForeachLoop.td
@@ -7,7 +7,7 @@ class Register<string name, int idx> {
// CHECK-NOT: !strconcat
-foreach i = 0-3 in
+foreach i = 0...3 in
def Q#i : Register<"Q"#i, i>;
// CHECK: def Q0
@@ -50,7 +50,7 @@ foreach i = [0, 1, 2, 3, 4, 5, 6, 7] in
// CHECK: string Name = "R7";
// CHECK: int Index = 7;
-foreach i = {0-3,9-7} in {
+foreach i = {0...3,9...7} in {
def S#i : Register<"Q"#i, i>;
def : Register<"T"#i, i>;
}
diff --git a/llvm/test/TableGen/HwModeEncodeDecode.td b/llvm/test/TableGen/HwModeEncodeDecode.td
index 1c9b86ff26a7..bac432271888 100644
--- a/llvm/test/TableGen/HwModeEncodeDecode.td
+++ b/llvm/test/TableGen/HwModeEncodeDecode.td
@@ -22,9 +22,9 @@ def fooTypeEncA : InstructionEncoding {
field bits<32> SoftFail = 0;
bits<32> Inst;
bits<8> factor;
- let Inst{7-0} = factor;
- let Inst{3-2} = 0b11;
- let Inst{1-0} = 0b00;
+ let Inst{7...0} = factor;
+ let Inst{3...2} = 0b11;
+ let Inst{1...0} = 0b00;
}
def fooTypeEncB : InstructionEncoding {
@@ -32,8 +32,8 @@ def fooTypeEncB : InstructionEncoding {
field bits<32> SoftFail = 0;
bits<32> Inst;
bits<8> factor;
- let Inst{15-8} = factor;
- let Inst{1-0} = 0b11;
+ let Inst{15...8} = factor;
+ let Inst{1...0} = 0b11;
}
let OutOperandList = (outs) in {
@@ -52,8 +52,8 @@ def bar: Instruction {
bits<32> Inst;
bits<32> SoftFail;
bits<8> factor;
- let Inst{31-24} = factor;
- let Inst{1-0} = 0b10;
+ let Inst{31...24} = factor;
+ let Inst{1...0} = 0b10;
let AsmString = "bar $factor";
}
diff --git a/llvm/test/TableGen/JSON.td b/llvm/test/TableGen/JSON.td
index 968c2577fa99..3fb2ec4014fb 100644
--- a/llvm/test/TableGen/JSON.td
+++ b/llvm/test/TableGen/JSON.td
@@ -97,8 +97,8 @@ def VarObj : Variables {
bits<2> undef_bits;
bits<4> ref_bits;
- let ref_bits{3-2} = 0b10;
- let ref_bits{1-0} = undef_bits{1-0};
+ let ref_bits{3...2} = 0b10;
+ let ref_bits{1...0} = undef_bits{1...0};
// CHECK: data['VarObj']['ref_bits'][3] == 1
// CHECK: data['VarObj']['ref_bits'][2] == 0
// CHECK: data['VarObj']['ref_bits'][1]['kind'] == 'varbit'
diff --git a/llvm/test/TableGen/ListSlices.td b/llvm/test/TableGen/ListSlices.td
index cbb2326a95c0..2f40334798b2 100644
--- a/llvm/test/TableGen/ListSlices.td
+++ b/llvm/test/TableGen/ListSlices.td
@@ -6,12 +6,12 @@ def A {
}
def B {
- list<int> X = [10, 20, 30, 4, 1, 1231, 20] [2-4,2,2,0-6];
+ list<int> X = [10, 20, 30, 4, 1, 1231, 20] [2...4,2,2,0...6];
list<int> Y = X[4,5];
int Z = X[4];
- list<int> C = A.B[1-4];
+ list<int> C = A.B[1...4];
list<list<int>> AA = [X, Y];
diff --git a/llvm/test/TableGen/UnsetBitInit.td b/llvm/test/TableGen/UnsetBitInit.td
index 694847358f66..07e37e08efab 100644
--- a/llvm/test/TableGen/UnsetBitInit.td
+++ b/llvm/test/TableGen/UnsetBitInit.td
@@ -21,7 +21,7 @@ def A {
bit P;
bit Q;
- let Inst{7-2} = 0x3f;
+ let Inst{7...2} = 0x3f;
let Inst{1} = P;
let Inst{0} = Q;
@@ -34,7 +34,7 @@ class x {
}
class y<bits<2> B> : x {
- let A{21-20} = B;
+ let A{21...20} = B;
}
def z : y<{0,?}>;
diff --git a/llvm/test/TableGen/cond-let.td b/llvm/test/TableGen/cond-let.td
index 044878f2ab8e..4e46445cc327 100644
--- a/llvm/test/TableGen/cond-let.td
+++ b/llvm/test/TableGen/cond-let.td
@@ -11,13 +11,13 @@ class C<bits<3> x, bits<4> y, bit z> {
y{1}: x{1},
y{0}: x{2},
{1} :?);
- let n{10-9}= !cond(x{2}: y{3-2},
- x{1}: y{2-1},
- x{1}: y{1-0},
- {1} : ?);
- let n{8-6} = !cond(x{2}: 0b010, 1 : 0b110);
- let n{5-4} = !cond(x{1}: y{3-2}, 1 : {0, 1});
- let n{3-0} = !cond(x{0}: y{3-0}, 1 : {z, y{2}, y{1}, y{0}});
+ let n{10...9}= !cond(x{2}: y{3...2},
+ x{1}: y{2...1},
+ x{1}: y{1...0},
+ {1} : ?);
+ let n{8...6} = !cond(x{2}: 0b010, 1 : 0b110);
+ let n{5...4} = !cond(x{1}: y{3...2}, 1 : {0, 1});
+ let n{3...0} = !cond(x{0}: y{3...0}, 1 : {z, y{2}, y{1}, y{0}});
}
diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
index 0002614fd574..462bb3f2cd6d 100644
--- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -12,7 +12,7 @@ let Namespace = "TestNamespace" in {
def R0 : Register<"r0">;
-foreach i = 0-127 in {
+foreach i = 0...127 in {
def GPR#i : RegisterClass<"TestTarget", [i32], 32,
(add R0)>;
}
diff --git a/llvm/test/TableGen/defset.td b/llvm/test/TableGen/defset.td
index 3c5fb68ea7ef..ef9f54ba6e2d 100644
--- a/llvm/test/TableGen/defset.td
+++ b/llvm/test/TableGen/defset.td
@@ -40,7 +40,7 @@ multiclass C<int c> {
defset list<A> As = {
def A0 : A<1>;
- foreach i = 1-2 in {
+ foreach i = 1...2 in {
def A#i : A<!add(i, 1)>;
}
defset list<A> SubAs = {
diff --git a/llvm/test/TableGen/foreach-variable-range.td b/llvm/test/TableGen/foreach-variable-range.td
index 3ddb2c08ff20..2a576d247a35 100644
--- a/llvm/test/TableGen/foreach-variable-range.td
+++ b/llvm/test/TableGen/foreach-variable-range.td
@@ -13,84 +13,84 @@ def Constants : ConstantsImpl;
// CHECK-DAG: def var_bound_whitespaceA0
// CHECK-DAG: def var_bound_whitespaceA1
// CHECK-DAG: def var_bound_whitespaceA2
-foreach Index = Constants.Zero - Constants.Two in {
+foreach Index = Constants.Zero ... Constants.Two in {
def var_bound_whitespaceA#Index;
}
// CHECK-DAG: def var_bound_whitespaceB0
// CHECK-DAG: def var_bound_whitespaceB1
// CHECK-DAG: def var_bound_whitespaceB2
-foreach Index = Constants.Zero-Constants.Two in {
+foreach Index = Constants.Zero...Constants.Two in {
def var_bounds_whitespaceB#Index;
}
// CHECK-DAG: def var_bound_whitespaceC0
// CHECK-DAG: def var_bound_whitespaceC1
// CHECK-DAG: def var_bound_whitespaceC2
-foreach Index = Constants.Zero -Constants.Two in {
+foreach Index = Constants.Zero ...Constants.Two in {
def var_bounds_whitespaceC#Index;
}
// CHECK-DAG: def var_bound_whitespaceD0
// CHECK-DAG: def var_bound_whitespaceD1
// CHECK-DAG: def var_bound_whitespaceD2
-foreach Index = Constants.Zero- Constants.Two in {
+foreach Index = Constants.Zero... Constants.Two in {
def var_bounds_whitespaceD#Index;
}
// CHECK-DAG: def const_lower_whitespaceA0
// CHECK-DAG: def const_lower_whitespaceA1
// CHECK-DAG: def const_lower_whitespaceA2
-foreach Index = 0 - Constants.Two in {
+foreach Index = 0 ... Constants.Two in {
def const_lower_whitespaceA#Index;
}
// CHECK-DAG: def const_lower_whitespaceB0
// CHECK-DAG: def const_lower_whitespaceB1
// CHECK-DAG: def const_lower_whitespaceB2
-foreach Index = 0-Constants.Two in {
+foreach Index = 0...Constants.Two in {
def const_lower_whitespaceB#Index;
}
// CHECK-DAG: def const_lower_whitespaceC0
// CHECK-DAG: def const_lower_whitespaceC1
// CHECK-DAG: def const_lower_whitespaceC2
-foreach Index = 0 -Constants.Two in {
+foreach Index = 0 ...Constants.Two in {
def const_lower_whitespaceC#Index;
}
// CHECK-DAG: def const_lower_whitespaceD0
// CHECK-DAG: def const_lower_whitespaceD1
// CHECK-DAG: def const_lower_whitespaceD2
-foreach Index = 0- Constants.Two in {
+foreach Index = 0... Constants.Two in {
def const_lower_whitespaceD#Index;
}
// CHECK-DAG: def const_upper_whitespaceA0
// CHECK-DAG: def const_upper_whitespaceA1
// CHECK-DAG: def const_upper_whitespaceA2
-foreach Index = Constants.Zero - 2 in {
+foreach Index = Constants.Zero ... 2 in {
def const_upper_whitespaceA#Index;
}
// CHECK-DAG: def const_upper_whitespaceB0
// CHECK-DAG: def const_upper_whitespaceB1
// CHECK-DAG: def const_upper_whitespaceB2
-foreach Index = Constants.Zero-2 in {
+foreach Index = Constants.Zero...2 in {
def const_upper_whitespaceB#Index;
}
// CHECK-DAG: def const_upper_whitespaceC0
// CHECK-DAG: def const_upper_whitespaceC1
// CHECK-DAG: def const_upper_whitespaceC2
-foreach Index = Constants.Zero -2 in {
+foreach Index = Constants.Zero ...2 in {
def const_upper_whitespaceC#Index;
}
// CHECK-DAG: def const_upper_whitespaceD0
// CHECK-DAG: def const_upper_whitespaceD1
// CHECK-DAG: def const_upper_whitespaceD2
-foreach Index = Constants.Zero- 2 in {
+foreach Index = Constants.Zero... 2 in {
def const_upper_whitespaceD#Index;
}
@@ -98,7 +98,7 @@ foreach Index = Constants.Zero- 2 in {
// CHECK-DAG: def multi_rangeA1
// CHECK-DAG: def multi_rangeA2
// CHECK-DAG: def multi_rangeA3
-foreach Index = {Constants.Zero-Constants.One, Constants.Two-Constants.Three} in {
+foreach Index = {Constants.Zero...Constants.One, Constants.Two...Constants.Three} in {
def multi_rangeA#Index;
}
@@ -107,7 +107,7 @@ foreach Index = {Constants.Zero-Constants.One, Constants.Two-Constants.Three} in
// CHECK-DAG: def multi_rangeB3
// CHECK-DAG: def multi_rangeB4
// CHECK-DAG: def multi_rangeB5
-foreach Index = {0-Constants.One, Constants.Three-Constants.Five} in {
+foreach Index = {0...Constants.One, Constants.Three...Constants.Five} in {
def multi_rangeB#Index;
}
@@ -115,7 +115,7 @@ foreach Index = {0-Constants.One, Constants.Three-Constants.Five} in {
// CHECK-DAG: def multi_rangeC1
// CHECK-DAG: def multi_rangeC2
// CHECK-DAG: def multi_rangeC3
-foreach Index = {0-Constants.One, 2-Constants.Three} in {
+foreach Index = {0...Constants.One, 2...Constants.Three} in {
def multi_rangeC#Index;
}
@@ -123,6 +123,6 @@ foreach Index = {0-Constants.One, 2-Constants.Three} in {
// CHECK-DAG: def multi_rangeD1
// CHECK-DAG: def multi_rangeD2
// CHECK-DAG: def multi_rangeD3
-foreach Index = {0-1, Constants.Two-3} in {
+foreach Index = {0...1, Constants.Two...3} in {
def multi_rangeD#Index;
}
diff --git a/llvm/test/TableGen/if.td b/llvm/test/TableGen/if.td
index a6af59e72830..1fbee6966ff3 100644
--- a/llvm/test/TableGen/if.td
+++ b/llvm/test/TableGen/if.td
@@ -11,12 +11,12 @@ class C<bits<3> x, bits<4> y, bit z> {
!if(y{2}, x{0},
!if(y{1}, x{1},
!if(y{0}, x{2}, ?))));
- let n{10-9}= !if(x{2}, y{3-2},
- !if(x{1}, y{2-1},
- !if(x{0}, y{1-0}, ?)));
- let n{8-6} = !if(x{2}, 0b010, 0b110);
- let n{5-4} = !if(x{1}, y{3-2}, {0, 1});
- let n{3-0} = !if(x{0}, y{3-0}, {z, y{2}, y{1}, y{0}});
+ let n{10...9}= !if(x{2}, y{3...2},
+ !if(x{1}, y{2...1},
+ !if(x{0}, y{1...0}, ?)));
+ let n{8...6} = !if(x{2}, 0b010, 0b110);
+ let n{5...4} = !if(x{1}, y{3...2}, {0, 1});
+ let n{3...0} = !if(x{0}, y{3...0}, {z, y{2}, y{1}, y{0}});
}
def C1 : C<{1, 0, 1}, {0, 1, 0, 1}, 0>;
diff --git a/llvm/test/TableGen/ifstmt.td b/llvm/test/TableGen/ifstmt.td
index 22354310e7ba..5c0093a9a9ea 100644
--- a/llvm/test/TableGen/ifstmt.td
+++ b/llvm/test/TableGen/ifstmt.td
@@ -15,7 +15,7 @@ if 1 then def aYes;
// CHECK: def bNotThree2
// CHECK: def bNotThree4
// CHECK: def bThree3
-foreach i = 1-4 in {
+foreach i = 1...4 in {
if !eq(i, 3) then {
def "bThree" # i;
} else {
@@ -61,8 +61,8 @@ defm c3: Multi<3>;
// CHECK-NOT: def dThenElse1
// CHECK-NOT: def dThenElse11
// CHECK: def dThenThen01
-foreach i = 0-1 in
- foreach j = 0-1 in
+foreach i = 0...1 in
+ foreach j = 0...1 in
if !eq(i,0) then
if !eq(j,1) then
def "dThenThen"#i#j;
diff --git a/llvm/test/TableGen/list-element-bitref.td b/llvm/test/TableGen/list-element-bitref.td
index 0f59b537fa6d..4aae62f329de 100644
--- a/llvm/test/TableGen/list-element-bitref.td
+++ b/llvm/test/TableGen/list-element-bitref.td
@@ -2,8 +2,8 @@
// XFAIL: vg_leak
class C<list<bits<4>> L> {
- bits<2> V0 = L[0]{1-0};
- bits<2> V1 = L[1]{3-2};
+ bits<2> V0 = L[0]{1...0};
+ bits<2> V1 = L[1]{3...2};
string V2 = !if(L[0]{0}, "Odd", "Even");
}
diff --git a/llvm/test/TableGen/range-lists.td b/llvm/test/TableGen/range-lists.td
index 82f4338323e5..85e0939f2ec0 100644
--- a/llvm/test/TableGen/range-lists.td
+++ b/llvm/test/TableGen/range-lists.td
@@ -1,7 +1,8 @@
// RUN: llvm-tblgen %s | FileCheck %s
// XFAIL: vg_leak
-// This file has tests for range lists and range pieces.
+// This file has tests for range lists and range pieces. Some use the
+// deprecated '-' range punctuation just to be sure it still works.
// These are tests for bits ranges.
diff --git a/llvm/test/TableGen/simplify-patfrag.td b/llvm/test/TableGen/simplify-patfrag.td
index 693658317d5d..904c29696a6e 100644
--- a/llvm/test/TableGen/simplify-patfrag.td
+++ b/llvm/test/TableGen/simplify-patfrag.td
@@ -9,7 +9,7 @@ def Demo : Target {
}
// Some registers which can hold ints or floats
-foreach i = 0-7 in
+foreach i = 0...7 in
def "R" # i: Register<"r" # i>;
def GPR : RegisterClass<"Demo", [i32, f32], 32, (sequence "R%u", 0, 7)>;
diff --git a/llvm/test/TableGen/trydecode-emission3.td b/llvm/test/TableGen/trydecode-emission3.td
index 8fc5150a0d8e..84ce4f9a749b 100644
--- a/llvm/test/TableGen/trydecode-emission3.td
+++ b/llvm/test/TableGen/trydecode-emission3.td
@@ -28,8 +28,8 @@ def InstBOp : Operand<i32> {
def InstB : TestInstruction {
bits<2> op;
- let Inst{7-2} = {0,0,0,0,0,0};
- let Inst{1-0} = op;
+ let Inst{7...2} = {0,0,0,0,0,0};
+ let Inst{1...0} = op;
let OutOperandList = (outs InstBOp:$op);
let AsmString = "InstB";
}
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