[llvm] 6cfd38d - [ARM] Fixup single source mla reductions.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 12 06:31:41 PDT 2020
Author: David Green
Date: 2020-09-12T14:31:26+01:00
New Revision: 6cfd38d03d5fc3cde929ebf82529415595e8ef8e
URL: https://github.com/llvm/llvm-project/commit/6cfd38d03d5fc3cde929ebf82529415595e8ef8e
DIFF: https://github.com/llvm/llvm-project/commit/6cfd38d03d5fc3cde929ebf82529415595e8ef8e.diff
LOG: [ARM] Fixup single source mla reductions.
This fixes a complication on top of D87276. If we are sign extending
around a mul with the two operands that are the same, instcombine will
helpfully convert one of the sext to a zext. Reverse that so that we
again generate a reduction.
Differnetial Revision: https://reviews.llvm.org/D87287
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 83d89de7b477..943dc467025d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14890,6 +14890,26 @@ static SDValue PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG,
if (IsPredVMLAV(MVT::i16, ISD::ZERO_EXTEND, {MVT::v16i8}, A, B, Mask))
return DAG.getNode(ISD::TRUNCATE, dl, ResVT,
DAG.getNode(ARMISD::VMLAVpu, dl, MVT::i32, A, B, Mask));
+
+ // Some complications. We can get a case where the two inputs of the mul are
+ // the same, then the output sext will have been helpfully converted to a
+ // zext. Turn it back.
+ SDValue Op = N0;
+ if (Op->getOpcode() == ISD::VSELECT)
+ Op = Op->getOperand(1);
+ if (Op->getOpcode() == ISD::ZERO_EXTEND &&
+ Op->getOperand(0)->getOpcode() == ISD::MUL) {
+ SDValue Mul = Op->getOperand(0);
+ if (Mul->getOperand(0) == Mul->getOperand(1) &&
+ Mul->getOperand(0)->getOpcode() == ISD::SIGN_EXTEND) {
+ SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, N0->getValueType(0), Mul);
+ if (Op != N0)
+ Ext = DAG.getNode(ISD::VSELECT, dl, N0->getValueType(0),
+ N0->getOperand(0), Ext, N0->getOperand(2));
+ return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext);
+ }
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
index 8cef85de3d95..b83b51b6f564 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
@@ -201,67 +201,7 @@ entry:
define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_sextzext(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: add_v8i16_v8i32_v8i64_sextzext:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.u16 r0, q0[0]
-; CHECK-NEXT: vmov.32 q1[0], r0
-; CHECK-NEXT: vmov.u16 r0, q0[1]
-; CHECK-NEXT: vmov.32 q1[1], r0
-; CHECK-NEXT: vmov.u16 r0, q0[2]
-; CHECK-NEXT: vmov.32 q1[2], r0
-; CHECK-NEXT: vmov.u16 r0, q0[3]
-; CHECK-NEXT: vmov.32 q1[3], r0
-; CHECK-NEXT: vmullb.s16 q2, q1, q1
-; CHECK-NEXT: vmov.i64 q1, #0xffffffff
-; CHECK-NEXT: vmov.f32 s12, s8
-; CHECK-NEXT: vmov.f32 s14, s9
-; CHECK-NEXT: vand q3, q3, q1
-; CHECK-NEXT: vmov r2, s14
-; CHECK-NEXT: vmov r3, s12
-; CHECK-NEXT: vmov r0, s15
-; CHECK-NEXT: vmov r1, s13
-; CHECK-NEXT: vmov.f32 s12, s10
-; CHECK-NEXT: vmov.f32 s14, s11
-; CHECK-NEXT: vand q2, q3, q1
-; CHECK-NEXT: adds r2, r2, r3
-; CHECK-NEXT: vmov r3, s8
-; CHECK-NEXT: adcs r0, r1
-; CHECK-NEXT: vmov r1, s9
-; CHECK-NEXT: adds r2, r2, r3
-; CHECK-NEXT: vmov r3, s10
-; CHECK-NEXT: adcs r0, r1
-; CHECK-NEXT: vmov r1, s11
-; CHECK-NEXT: adds r2, r2, r3
-; CHECK-NEXT: adcs r0, r1
-; CHECK-NEXT: vmov.u16 r1, q0[4]
-; CHECK-NEXT: vmov.32 q2[0], r1
-; CHECK-NEXT: vmov.u16 r1, q0[5]
-; CHECK-NEXT: vmov.32 q2[1], r1
-; CHECK-NEXT: vmov.u16 r1, q0[6]
-; CHECK-NEXT: vmov.32 q2[2], r1
-; CHECK-NEXT: vmov.u16 r1, q0[7]
-; CHECK-NEXT: vmov.32 q2[3], r1
-; CHECK-NEXT: vmullb.s16 q0, q2, q2
-; CHECK-NEXT: vmov.f32 s8, s0
-; CHECK-NEXT: vmov.f32 s10, s1
-; CHECK-NEXT: vand q2, q2, q1
-; CHECK-NEXT: vmov r3, s8
-; CHECK-NEXT: vmov r1, s9
-; CHECK-NEXT: adds r2, r2, r3
-; CHECK-NEXT: vmov r3, s10
-; CHECK-NEXT: adcs r0, r1
-; CHECK-NEXT: vmov r1, s11
-; CHECK-NEXT: vmov.f32 s8, s2
-; CHECK-NEXT: vmov.f32 s10, s3
-; CHECK-NEXT: vand q0, q2, q1
-; CHECK-NEXT: adds r2, r2, r3
-; CHECK-NEXT: vmov r3, s0
-; CHECK-NEXT: adcs r0, r1
-; CHECK-NEXT: vmov r1, s1
-; CHECK-NEXT: adds r2, r2, r3
-; CHECK-NEXT: vmov r3, s3
-; CHECK-NEXT: adcs r1, r0
-; CHECK-NEXT: vmov r0, s2
-; CHECK-NEXT: adds r0, r0, r2
-; CHECK-NEXT: adcs r1, r3
+; CHECK-NEXT: vmlalv.s16 r0, r1, q0, q0
; CHECK-NEXT: bx lr
entry:
%xx = sext <8 x i16> %x to <8 x i32>
@@ -371,80 +311,7 @@ entry:
define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_sextzext(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: add_v16i8_v16i16_v16i32_sextzext:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.u8 r0, q0[8]
-; CHECK-NEXT: vmov.16 q1[0], r0
-; CHECK-NEXT: vmov.u8 r0, q0[9]
-; CHECK-NEXT: vmov.16 q1[1], r0
-; CHECK-NEXT: vmov.u8 r0, q0[10]
-; CHECK-NEXT: vmov.16 q1[2], r0
-; CHECK-NEXT: vmov.u8 r0, q0[11]
-; CHECK-NEXT: vmov.16 q1[3], r0
-; CHECK-NEXT: vmov.u8 r0, q0[12]
-; CHECK-NEXT: vmov.16 q1[4], r0
-; CHECK-NEXT: vmov.u8 r0, q0[13]
-; CHECK-NEXT: vmov.16 q1[5], r0
-; CHECK-NEXT: vmov.u8 r0, q0[14]
-; CHECK-NEXT: vmov.16 q1[6], r0
-; CHECK-NEXT: vmov.u8 r0, q0[15]
-; CHECK-NEXT: vmov.16 q1[7], r0
-; CHECK-NEXT: vmullb.s8 q1, q1, q1
-; CHECK-NEXT: vmov.u16 r0, q1[4]
-; CHECK-NEXT: vmov.32 q2[0], r0
-; CHECK-NEXT: vmov.u16 r0, q1[5]
-; CHECK-NEXT: vmov.32 q2[1], r0
-; CHECK-NEXT: vmov.u16 r0, q1[6]
-; CHECK-NEXT: vmov.32 q2[2], r0
-; CHECK-NEXT: vmov.u16 r0, q1[7]
-; CHECK-NEXT: vmov.32 q2[3], r0
-; CHECK-NEXT: vmov.u8 r0, q0[0]
-; CHECK-NEXT: vmov.16 q3[0], r0
-; CHECK-NEXT: vmov.u8 r0, q0[1]
-; CHECK-NEXT: vmov.16 q3[1], r0
-; CHECK-NEXT: vmov.u8 r0, q0[2]
-; CHECK-NEXT: vmov.16 q3[2], r0
-; CHECK-NEXT: vmov.u8 r0, q0[3]
-; CHECK-NEXT: vmov.16 q3[3], r0
-; CHECK-NEXT: vmov.u8 r0, q0[4]
-; CHECK-NEXT: vmov.16 q3[4], r0
-; CHECK-NEXT: vmov.u8 r0, q0[5]
-; CHECK-NEXT: vmov.16 q3[5], r0
-; CHECK-NEXT: vmov.u8 r0, q0[6]
-; CHECK-NEXT: vmov.16 q3[6], r0
-; CHECK-NEXT: vmov.u8 r0, q0[7]
-; CHECK-NEXT: vmov.16 q3[7], r0
-; CHECK-NEXT: vmovlb.u16 q2, q2
-; CHECK-NEXT: vmullb.s8 q0, q3, q3
-; CHECK-NEXT: vmov.u16 r0, q0[4]
-; CHECK-NEXT: vmov.32 q3[0], r0
-; CHECK-NEXT: vmov.u16 r0, q0[5]
-; CHECK-NEXT: vmov.32 q3[1], r0
-; CHECK-NEXT: vmov.u16 r0, q0[6]
-; CHECK-NEXT: vmov.32 q3[2], r0
-; CHECK-NEXT: vmov.u16 r0, q0[7]
-; CHECK-NEXT: vmov.32 q3[3], r0
-; CHECK-NEXT: vmov.u16 r0, q1[0]
-; CHECK-NEXT: vmovlb.u16 q3, q3
-; CHECK-NEXT: vadd.i32 q2, q3, q2
-; CHECK-NEXT: vmov.32 q3[0], r0
-; CHECK-NEXT: vmov.u16 r0, q1[1]
-; CHECK-NEXT: vmov.32 q3[1], r0
-; CHECK-NEXT: vmov.u16 r0, q1[2]
-; CHECK-NEXT: vmov.32 q3[2], r0
-; CHECK-NEXT: vmov.u16 r0, q1[3]
-; CHECK-NEXT: vmov.32 q3[3], r0
-; CHECK-NEXT: vmov.u16 r0, q0[0]
-; CHECK-NEXT: vmovlb.u16 q1, q3
-; CHECK-NEXT: vmov.32 q3[0], r0
-; CHECK-NEXT: vmov.u16 r0, q0[1]
-; CHECK-NEXT: vmov.32 q3[1], r0
-; CHECK-NEXT: vmov.u16 r0, q0[2]
-; CHECK-NEXT: vmov.32 q3[2], r0
-; CHECK-NEXT: vmov.u16 r0, q0[3]
-; CHECK-NEXT: vmov.32 q3[3], r0
-; CHECK-NEXT: vmovlb.u16 q0, q3
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: vadd.i32 q0, q0, q2
-; CHECK-NEXT: vaddv.u32 r0, q0
+; CHECK-NEXT: vmlav.s8 r0, q0, q0
; CHECK-NEXT: bx lr
entry:
%xx = sext <16 x i8> %x to <16 x i16>
@@ -1238,72 +1105,8 @@ entry:
define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_acc_sextzext(<8 x i16> %x, <8 x i16> %y, i64 %a) {
; CHECK-LABEL: add_v8i16_v8i32_v8i64_acc_sextzext:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, lr}
-; CHECK-NEXT: push {r4, lr}
-; CHECK-NEXT: vmov.u16 r2, q0[0]
-; CHECK-NEXT: vmov.32 q1[0], r2
-; CHECK-NEXT: vmov.u16 r2, q0[1]
-; CHECK-NEXT: vmov.32 q1[1], r2
-; CHECK-NEXT: vmov.u16 r2, q0[2]
-; CHECK-NEXT: vmov.32 q1[2], r2
-; CHECK-NEXT: vmov.u16 r2, q0[3]
-; CHECK-NEXT: vmov.32 q1[3], r2
-; CHECK-NEXT: vmullb.s16 q2, q1, q1
-; CHECK-NEXT: vmov.i64 q1, #0xffffffff
-; CHECK-NEXT: vmov.f32 s12, s8
-; CHECK-NEXT: vmov.f32 s14, s9
-; CHECK-NEXT: vand q3, q3, q1
-; CHECK-NEXT: vmov r2, s14
-; CHECK-NEXT: vmov r3, s12
-; CHECK-NEXT: vmov r12, s15
-; CHECK-NEXT: vmov lr, s13
-; CHECK-NEXT: vmov.f32 s12, s10
-; CHECK-NEXT: vmov.f32 s14, s11
-; CHECK-NEXT: vand q2, q3, q1
-; CHECK-NEXT: adds r4, r3, r2
-; CHECK-NEXT: vmov r3, s8
-; CHECK-NEXT: vmov r2, s9
-; CHECK-NEXT: adc.w r12, r12, lr
-; CHECK-NEXT: adds r3, r3, r4
-; CHECK-NEXT: vmov r4, s11
-; CHECK-NEXT: adc.w r12, r12, r2
-; CHECK-NEXT: vmov r2, s10
-; CHECK-NEXT: adds.w lr, r3, r2
-; CHECK-NEXT: adc.w r3, r12, r4
-; CHECK-NEXT: vmov.u16 r4, q0[4]
-; CHECK-NEXT: vmov.32 q2[0], r4
-; CHECK-NEXT: vmov.u16 r4, q0[5]
-; CHECK-NEXT: vmov.32 q2[1], r4
-; CHECK-NEXT: vmov.u16 r4, q0[6]
-; CHECK-NEXT: vmov.32 q2[2], r4
-; CHECK-NEXT: vmov.u16 r4, q0[7]
-; CHECK-NEXT: vmov.32 q2[3], r4
-; CHECK-NEXT: vmullb.s16 q0, q2, q2
-; CHECK-NEXT: vmov.f32 s8, s0
-; CHECK-NEXT: vmov.f32 s10, s1
-; CHECK-NEXT: vand q2, q2, q1
-; CHECK-NEXT: vmov r2, s8
-; CHECK-NEXT: vmov r4, s9
-; CHECK-NEXT: adds.w r12, lr, r2
-; CHECK-NEXT: vmov r2, s10
-; CHECK-NEXT: adcs r3, r4
-; CHECK-NEXT: vmov r4, s11
-; CHECK-NEXT: vmov.f32 s8, s2
-; CHECK-NEXT: vmov.f32 s10, s3
-; CHECK-NEXT: vand q0, q2, q1
-; CHECK-NEXT: adds.w r12, r12, r2
-; CHECK-NEXT: vmov r2, s0
-; CHECK-NEXT: adcs r3, r4
-; CHECK-NEXT: vmov r4, s1
-; CHECK-NEXT: adds.w r12, r12, r2
-; CHECK-NEXT: vmov r2, s2
-; CHECK-NEXT: adcs r3, r4
-; CHECK-NEXT: vmov r4, s3
-; CHECK-NEXT: adds.w r2, r2, r12
-; CHECK-NEXT: adcs r3, r4
-; CHECK-NEXT: adds r0, r0, r2
-; CHECK-NEXT: adcs r1, r3
-; CHECK-NEXT: pop {r4, pc}
+; CHECK-NEXT: vmlalva.s16 r0, r1, q0, q0
+; CHECK-NEXT: bx lr
entry:
%xx = sext <8 x i16> %x to <8 x i32>
%m = mul <8 x i32> %xx, %xx
@@ -1427,80 +1230,7 @@ entry:
define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_acc_sextzext(<16 x i8> %x, i32 %a) {
; CHECK-LABEL: add_v16i8_v16i16_v16i32_acc_sextzext:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.u8 r1, q0[8]
-; CHECK-NEXT: vmov.16 q1[0], r1
-; CHECK-NEXT: vmov.u8 r1, q0[9]
-; CHECK-NEXT: vmov.16 q1[1], r1
-; CHECK-NEXT: vmov.u8 r1, q0[10]
-; CHECK-NEXT: vmov.16 q1[2], r1
-; CHECK-NEXT: vmov.u8 r1, q0[11]
-; CHECK-NEXT: vmov.16 q1[3], r1
-; CHECK-NEXT: vmov.u8 r1, q0[12]
-; CHECK-NEXT: vmov.16 q1[4], r1
-; CHECK-NEXT: vmov.u8 r1, q0[13]
-; CHECK-NEXT: vmov.16 q1[5], r1
-; CHECK-NEXT: vmov.u8 r1, q0[14]
-; CHECK-NEXT: vmov.16 q1[6], r1
-; CHECK-NEXT: vmov.u8 r1, q0[15]
-; CHECK-NEXT: vmov.16 q1[7], r1
-; CHECK-NEXT: vmullb.s8 q1, q1, q1
-; CHECK-NEXT: vmov.u16 r1, q1[4]
-; CHECK-NEXT: vmov.32 q2[0], r1
-; CHECK-NEXT: vmov.u16 r1, q1[5]
-; CHECK-NEXT: vmov.32 q2[1], r1
-; CHECK-NEXT: vmov.u16 r1, q1[6]
-; CHECK-NEXT: vmov.32 q2[2], r1
-; CHECK-NEXT: vmov.u16 r1, q1[7]
-; CHECK-NEXT: vmov.32 q2[3], r1
-; CHECK-NEXT: vmov.u8 r1, q0[0]
-; CHECK-NEXT: vmov.16 q3[0], r1
-; CHECK-NEXT: vmov.u8 r1, q0[1]
-; CHECK-NEXT: vmov.16 q3[1], r1
-; CHECK-NEXT: vmov.u8 r1, q0[2]
-; CHECK-NEXT: vmov.16 q3[2], r1
-; CHECK-NEXT: vmov.u8 r1, q0[3]
-; CHECK-NEXT: vmov.16 q3[3], r1
-; CHECK-NEXT: vmov.u8 r1, q0[4]
-; CHECK-NEXT: vmov.16 q3[4], r1
-; CHECK-NEXT: vmov.u8 r1, q0[5]
-; CHECK-NEXT: vmov.16 q3[5], r1
-; CHECK-NEXT: vmov.u8 r1, q0[6]
-; CHECK-NEXT: vmov.16 q3[6], r1
-; CHECK-NEXT: vmov.u8 r1, q0[7]
-; CHECK-NEXT: vmov.16 q3[7], r1
-; CHECK-NEXT: vmovlb.u16 q2, q2
-; CHECK-NEXT: vmullb.s8 q0, q3, q3
-; CHECK-NEXT: vmov.u16 r1, q0[4]
-; CHECK-NEXT: vmov.32 q3[0], r1
-; CHECK-NEXT: vmov.u16 r1, q0[5]
-; CHECK-NEXT: vmov.32 q3[1], r1
-; CHECK-NEXT: vmov.u16 r1, q0[6]
-; CHECK-NEXT: vmov.32 q3[2], r1
-; CHECK-NEXT: vmov.u16 r1, q0[7]
-; CHECK-NEXT: vmov.32 q3[3], r1
-; CHECK-NEXT: vmov.u16 r1, q1[0]
-; CHECK-NEXT: vmovlb.u16 q3, q3
-; CHECK-NEXT: vadd.i32 q2, q3, q2
-; CHECK-NEXT: vmov.32 q3[0], r1
-; CHECK-NEXT: vmov.u16 r1, q1[1]
-; CHECK-NEXT: vmov.32 q3[1], r1
-; CHECK-NEXT: vmov.u16 r1, q1[2]
-; CHECK-NEXT: vmov.32 q3[2], r1
-; CHECK-NEXT: vmov.u16 r1, q1[3]
-; CHECK-NEXT: vmov.32 q3[3], r1
-; CHECK-NEXT: vmov.u16 r1, q0[0]
-; CHECK-NEXT: vmovlb.u16 q1, q3
-; CHECK-NEXT: vmov.32 q3[0], r1
-; CHECK-NEXT: vmov.u16 r1, q0[1]
-; CHECK-NEXT: vmov.32 q3[1], r1
-; CHECK-NEXT: vmov.u16 r1, q0[2]
-; CHECK-NEXT: vmov.32 q3[2], r1
-; CHECK-NEXT: vmov.u16 r1, q0[3]
-; CHECK-NEXT: vmov.32 q3[3], r1
-; CHECK-NEXT: vmovlb.u16 q0, q3
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: vadd.i32 q0, q0, q2
-; CHECK-NEXT: vaddva.u32 r0, q0
+; CHECK-NEXT: vmlava.s8 r0, q0, q0
; CHECK-NEXT: bx lr
entry:
%xx = sext <16 x i8> %x to <16 x i16>
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
index fd268fd4c5a9..02d124890c6b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
@@ -273,130 +273,8 @@ entry:
define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_sextzext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) {
; CHECK-LABEL: add_v8i16_v8i32_v8i64_sextzext:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9, d10, d11}
-; CHECK-NEXT: vpush {d8, d9, d10, d11}
-; CHECK-NEXT: vmov.i8 q1, #0x0
-; CHECK-NEXT: vmov.i8 q3, #0xff
-; CHECK-NEXT: vcmp.i16 eq, q2, zr
-; CHECK-NEXT: vpsel q2, q3, q1
-; CHECK-NEXT: vmov.u16 r0, q2[0]
-; CHECK-NEXT: vmov.32 q1[0], r0
-; CHECK-NEXT: vmov.u16 r0, q2[1]
-; CHECK-NEXT: vmov.32 q1[1], r0
-; CHECK-NEXT: vmov.u16 r0, q2[2]
-; CHECK-NEXT: vmov.32 q1[2], r0
-; CHECK-NEXT: vmov.u16 r0, q2[3]
-; CHECK-NEXT: vmov.32 q1[3], r0
-; CHECK-NEXT: vcmp.i32 ne, q1, zr
-; CHECK-NEXT: vmrs r0, p0
-; CHECK-NEXT: and r1, r0, #1
-; CHECK-NEXT: rsbs r1, r1, #0
-; CHECK-NEXT: vmov.32 q4[0], r1
-; CHECK-NEXT: vmov.32 q4[1], r1
-; CHECK-NEXT: ubfx r1, r0, #4, #1
-; CHECK-NEXT: rsbs r1, r1, #0
-; CHECK-NEXT: vmov.32 q4[2], r1
-; CHECK-NEXT: vmov.32 q4[3], r1
-; CHECK-NEXT: vmov.u16 r1, q0[0]
-; CHECK-NEXT: vmov.32 q1[0], r1
-; CHECK-NEXT: vmov.u16 r1, q0[1]
-; CHECK-NEXT: vmov.32 q1[1], r1
-; CHECK-NEXT: vmov.u16 r1, q0[2]
-; CHECK-NEXT: vmov.32 q1[2], r1
-; CHECK-NEXT: vmov.u16 r1, q0[3]
-; CHECK-NEXT: vmov.32 q1[3], r1
-; CHECK-NEXT: vmullb.s16 q3, q1, q1
-; CHECK-NEXT: vmov.i64 q1, #0xffffffff
-; CHECK-NEXT: vmov.f32 s20, s12
-; CHECK-NEXT: vmov.f32 s22, s13
-; CHECK-NEXT: vand q5, q5, q1
-; CHECK-NEXT: vand q4, q5, q4
-; CHECK-NEXT: vmov.f32 s20, s14
-; CHECK-NEXT: vmov r3, s18
-; CHECK-NEXT: vmov r1, s16
-; CHECK-NEXT: vmov r12, s19
-; CHECK-NEXT: vmov r2, s17
-; CHECK-NEXT: vmov.f32 s22, s15
-; CHECK-NEXT: vand q3, q5, q1
-; CHECK-NEXT: adds r1, r1, r3
-; CHECK-NEXT: ubfx r3, r0, #8, #1
-; CHECK-NEXT: rsb.w r3, r3, #0
-; CHECK-NEXT: ubfx r0, r0, #12, #1
-; CHECK-NEXT: vmov.32 q4[0], r3
-; CHECK-NEXT: rsb.w r0, r0, #0
-; CHECK-NEXT: vmov.32 q4[1], r3
-; CHECK-NEXT: adc.w r2, r2, r12
-; CHECK-NEXT: vmov.32 q4[2], r0
-; CHECK-NEXT: vmov.32 q4[3], r0
-; CHECK-NEXT: vand q3, q3, q4
-; CHECK-NEXT: vmov r3, s12
-; CHECK-NEXT: vmov r0, s13
-; CHECK-NEXT: adds r1, r1, r3
-; CHECK-NEXT: vmov r3, s15
-; CHECK-NEXT: adcs r2, r0
-; CHECK-NEXT: vmov r0, s14
-; CHECK-NEXT: adds.w r12, r1, r0
-; CHECK-NEXT: adc.w r1, r2, r3
-; CHECK-NEXT: vmov.u16 r2, q2[4]
-; CHECK-NEXT: vmov.32 q3[0], r2
-; CHECK-NEXT: vmov.u16 r2, q2[5]
-; CHECK-NEXT: vmov.32 q3[1], r2
-; CHECK-NEXT: vmov.u16 r2, q2[6]
-; CHECK-NEXT: vmov.32 q3[2], r2
-; CHECK-NEXT: vmov.u16 r2, q2[7]
-; CHECK-NEXT: vmov.32 q3[3], r2
-; CHECK-NEXT: vcmp.i32 ne, q3, zr
-; CHECK-NEXT: vmrs r2, p0
-; CHECK-NEXT: and r3, r2, #1
-; CHECK-NEXT: rsbs r3, r3, #0
-; CHECK-NEXT: vmov.32 q2[0], r3
-; CHECK-NEXT: vmov.32 q2[1], r3
-; CHECK-NEXT: ubfx r3, r2, #4, #1
-; CHECK-NEXT: rsbs r3, r3, #0
-; CHECK-NEXT: vmov.32 q2[2], r3
-; CHECK-NEXT: vmov.32 q2[3], r3
-; CHECK-NEXT: vmov.u16 r3, q0[4]
-; CHECK-NEXT: vmov.32 q3[0], r3
-; CHECK-NEXT: vmov.u16 r3, q0[5]
-; CHECK-NEXT: vmov.32 q3[1], r3
-; CHECK-NEXT: vmov.u16 r3, q0[6]
-; CHECK-NEXT: vmov.32 q3[2], r3
-; CHECK-NEXT: vmov.u16 r3, q0[7]
-; CHECK-NEXT: vmov.32 q3[3], r3
-; CHECK-NEXT: vmullb.s16 q0, q3, q3
-; CHECK-NEXT: vmov.f32 s12, s0
-; CHECK-NEXT: vmov.f32 s14, s1
-; CHECK-NEXT: vand q3, q3, q1
-; CHECK-NEXT: vand q2, q3, q2
-; CHECK-NEXT: vmov.f32 s12, s2
-; CHECK-NEXT: vmov r0, s8
-; CHECK-NEXT: vmov r3, s9
-; CHECK-NEXT: vmov.f32 s14, s3
-; CHECK-NEXT: vand q0, q3, q1
-; CHECK-NEXT: adds.w r12, r12, r0
-; CHECK-NEXT: vmov r0, s10
-; CHECK-NEXT: adcs r1, r3
-; CHECK-NEXT: vmov r3, s11
-; CHECK-NEXT: adds.w r0, r0, r12
-; CHECK-NEXT: adcs r1, r3
-; CHECK-NEXT: ubfx r3, r2, #8, #1
-; CHECK-NEXT: rsbs r3, r3, #0
-; CHECK-NEXT: ubfx r2, r2, #12, #1
-; CHECK-NEXT: vmov.32 q2[0], r3
-; CHECK-NEXT: rsbs r2, r2, #0
-; CHECK-NEXT: vmov.32 q2[1], r3
-; CHECK-NEXT: vmov.32 q2[2], r2
-; CHECK-NEXT: vmov.32 q2[3], r2
-; CHECK-NEXT: vand q0, q0, q2
-; CHECK-NEXT: vmov r3, s0
-; CHECK-NEXT: vmov r2, s1
-; CHECK-NEXT: adds r0, r0, r3
-; CHECK-NEXT: vmov r3, s2
-; CHECK-NEXT: adcs r1, r2
-; CHECK-NEXT: vmov r2, s3
-; CHECK-NEXT: adds r0, r0, r3
-; CHECK-NEXT: adcs r1, r2
-; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-NEXT: vpt.i16 eq, q2, zr
+; CHECK-NEXT: vmlalvt.s16 r0, r1, q0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i16> %b, zeroinitializer
@@ -580,174 +458,8 @@ entry:
define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_sextzext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) {
; CHECK-LABEL: add_v16i8_v16i16_v16i32_sextzext:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: .pad #32
-; CHECK-NEXT: sub sp, #32
-; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: vcmp.i8 eq, q2, zr
-; CHECK-NEXT: vmov.i8 q2, #0xff
-; CHECK-NEXT: vmov.i8 q0, #0x0
-; CHECK-NEXT: vpsel q1, q2, q0
-; CHECK-NEXT: vmov q3, q2
-; CHECK-NEXT: vmov.u8 r0, q1[0]
-; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill
-; CHECK-NEXT: vmov.16 q2[0], r0
-; CHECK-NEXT: vmov.u8 r0, q1[1]
-; CHECK-NEXT: vmov.16 q2[1], r0
-; CHECK-NEXT: vmov.u8 r0, q1[2]
-; CHECK-NEXT: vmov.16 q2[2], r0
-; CHECK-NEXT: vmov.u8 r0, q1[3]
-; CHECK-NEXT: vmov.16 q2[3], r0
-; CHECK-NEXT: vmov.u8 r0, q1[4]
-; CHECK-NEXT: vmov.16 q2[4], r0
-; CHECK-NEXT: vmov.u8 r0, q1[5]
-; CHECK-NEXT: vmov.16 q2[5], r0
-; CHECK-NEXT: vmov.u8 r0, q1[6]
-; CHECK-NEXT: vmov.16 q2[6], r0
-; CHECK-NEXT: vmov.u8 r0, q1[7]
-; CHECK-NEXT: vmov.16 q2[7], r0
-; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
-; CHECK-NEXT: vcmp.i16 ne, q2, zr
-; CHECK-NEXT: vmov.i32 q6, #0x0
-; CHECK-NEXT: vpsel q5, q3, q0
-; CHECK-NEXT: vmov q7, q6
-; CHECK-NEXT: vmov.u16 r0, q5[4]
-; CHECK-NEXT: vmov.i32 q2, #0xffff
-; CHECK-NEXT: vmov.32 q0[0], r0
-; CHECK-NEXT: vmov.u16 r0, q5[5]
-; CHECK-NEXT: vmov.32 q0[1], r0
-; CHECK-NEXT: vmov.u16 r0, q5[6]
-; CHECK-NEXT: vmov.32 q0[2], r0
-; CHECK-NEXT: vmov.u16 r0, q5[7]
-; CHECK-NEXT: vmov.32 q0[3], r0
-; CHECK-NEXT: vmov.u8 r0, q4[0]
-; CHECK-NEXT: vmov.16 q3[0], r0
-; CHECK-NEXT: vmov.u8 r0, q4[1]
-; CHECK-NEXT: vmov.16 q3[1], r0
-; CHECK-NEXT: vmov.u8 r0, q4[2]
-; CHECK-NEXT: vmov.16 q3[2], r0
-; CHECK-NEXT: vmov.u8 r0, q4[3]
-; CHECK-NEXT: vmov.16 q3[3], r0
-; CHECK-NEXT: vmov.u8 r0, q4[4]
-; CHECK-NEXT: vmov.16 q3[4], r0
-; CHECK-NEXT: vmov.u8 r0, q4[5]
-; CHECK-NEXT: vmov.16 q3[5], r0
-; CHECK-NEXT: vmov.u8 r0, q4[6]
-; CHECK-NEXT: vmov.16 q3[6], r0
-; CHECK-NEXT: vmov.u8 r0, q4[7]
-; CHECK-NEXT: vmov.16 q3[7], r0
-; CHECK-NEXT: vcmp.i32 ne, q0, zr
-; CHECK-NEXT: vmullb.s8 q3, q3, q3
-; CHECK-NEXT: vmov.u16 r0, q3[4]
-; CHECK-NEXT: vmov.32 q0[0], r0
-; CHECK-NEXT: vmov.u16 r0, q3[5]
-; CHECK-NEXT: vmov.32 q0[1], r0
-; CHECK-NEXT: vmov.u16 r0, q3[6]
-; CHECK-NEXT: vmov.32 q0[2], r0
-; CHECK-NEXT: vmov.u16 r0, q3[7]
-; CHECK-NEXT: vmov.32 q0[3], r0
-; CHECK-NEXT: vmov.u8 r0, q1[8]
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vandt q7, q0, q2
-; CHECK-NEXT: vmov.16 q0[0], r0
-; CHECK-NEXT: vmov.u8 r0, q1[9]
-; CHECK-NEXT: vmov.16 q0[1], r0
-; CHECK-NEXT: vmov.u8 r0, q1[10]
-; CHECK-NEXT: vmov.16 q0[2], r0
-; CHECK-NEXT: vmov.u8 r0, q1[11]
-; CHECK-NEXT: vmov.16 q0[3], r0
-; CHECK-NEXT: vmov.u8 r0, q1[12]
-; CHECK-NEXT: vmov.16 q0[4], r0
-; CHECK-NEXT: vmov.u8 r0, q1[13]
-; CHECK-NEXT: vmov.16 q0[5], r0
-; CHECK-NEXT: vmov.u8 r0, q1[14]
-; CHECK-NEXT: vmov.16 q0[6], r0
-; CHECK-NEXT: vmov.u8 r0, q1[15]
-; CHECK-NEXT: vmov.16 q0[7], r0
-; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
-; CHECK-NEXT: vcmp.i16 ne, q0, zr
-; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT: vpsel q0, q1, q0
-; CHECK-NEXT: vmov.u16 r0, q0[4]
-; CHECK-NEXT: vmov.32 q1[0], r0
-; CHECK-NEXT: vmov.u16 r0, q0[5]
-; CHECK-NEXT: vmov.32 q1[1], r0
-; CHECK-NEXT: vmov.u16 r0, q0[6]
-; CHECK-NEXT: vmov.32 q1[2], r0
-; CHECK-NEXT: vmov.u16 r0, q0[7]
-; CHECK-NEXT: vmov.32 q1[3], r0
-; CHECK-NEXT: vmov.u8 r0, q4[8]
-; CHECK-NEXT: vcmp.i32 ne, q1, zr
-; CHECK-NEXT: vmov.16 q1[0], r0
-; CHECK-NEXT: vmov.u8 r0, q4[9]
-; CHECK-NEXT: vmov.16 q1[1], r0
-; CHECK-NEXT: vmov.u8 r0, q4[10]
-; CHECK-NEXT: vmov.16 q1[2], r0
-; CHECK-NEXT: vmov.u8 r0, q4[11]
-; CHECK-NEXT: vmov.16 q1[3], r0
-; CHECK-NEXT: vmov.u8 r0, q4[12]
-; CHECK-NEXT: vmov.16 q1[4], r0
-; CHECK-NEXT: vmov.u8 r0, q4[13]
-; CHECK-NEXT: vmov.16 q1[5], r0
-; CHECK-NEXT: vmov.u8 r0, q4[14]
-; CHECK-NEXT: vmov.16 q1[6], r0
-; CHECK-NEXT: vmov.u8 r0, q4[15]
-; CHECK-NEXT: vmov.16 q1[7], r0
-; CHECK-NEXT: vmullb.s8 q1, q1, q1
-; CHECK-NEXT: vmov.u16 r0, q1[4]
-; CHECK-NEXT: vmov.32 q4[0], r0
-; CHECK-NEXT: vmov.u16 r0, q1[5]
-; CHECK-NEXT: vmov.32 q4[1], r0
-; CHECK-NEXT: vmov.u16 r0, q1[6]
-; CHECK-NEXT: vmov.32 q4[2], r0
-; CHECK-NEXT: vmov.u16 r0, q1[7]
-; CHECK-NEXT: vmov.32 q4[3], r0
-; CHECK-NEXT: vmov.u16 r0, q5[0]
-; CHECK-NEXT: vmovlb.u16 q4, q4
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vaddt.i32 q7, q7, q4
-; CHECK-NEXT: vmov.32 q4[0], r0
-; CHECK-NEXT: vmov.u16 r0, q5[1]
-; CHECK-NEXT: vmov.32 q4[1], r0
-; CHECK-NEXT: vmov.u16 r0, q5[2]
-; CHECK-NEXT: vmov.32 q4[2], r0
-; CHECK-NEXT: vmov.u16 r0, q5[3]
-; CHECK-NEXT: vmov.32 q4[3], r0
-; CHECK-NEXT: vmov.u16 r0, q3[0]
-; CHECK-NEXT: vcmp.i32 ne, q4, zr
-; CHECK-NEXT: vmov.32 q4[0], r0
-; CHECK-NEXT: vmov.u16 r0, q3[1]
-; CHECK-NEXT: vmov.32 q4[1], r0
-; CHECK-NEXT: vmov.u16 r0, q3[2]
-; CHECK-NEXT: vmov.32 q4[2], r0
-; CHECK-NEXT: vmov.u16 r0, q3[3]
-; CHECK-NEXT: vmov.32 q4[3], r0
-; CHECK-NEXT: vmov.u16 r0, q0[0]
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vandt q6, q4, q2
-; CHECK-NEXT: vmov.32 q2[0], r0
-; CHECK-NEXT: vmov.u16 r0, q0[1]
-; CHECK-NEXT: vmov.32 q2[1], r0
-; CHECK-NEXT: vmov.u16 r0, q0[2]
-; CHECK-NEXT: vmov.32 q2[2], r0
-; CHECK-NEXT: vmov.u16 r0, q0[3]
-; CHECK-NEXT: vmov.32 q2[3], r0
-; CHECK-NEXT: vmov.u16 r0, q1[0]
-; CHECK-NEXT: vmov.32 q0[0], r0
-; CHECK-NEXT: vmov.u16 r0, q1[1]
-; CHECK-NEXT: vmov.32 q0[1], r0
-; CHECK-NEXT: vmov.u16 r0, q1[2]
-; CHECK-NEXT: vmov.32 q0[2], r0
-; CHECK-NEXT: vmov.u16 r0, q1[3]
-; CHECK-NEXT: vmov.32 q0[3], r0
-; CHECK-NEXT: vmovlb.u16 q0, q0
-; CHECK-NEXT: vpt.i32 ne, q2, zr
-; CHECK-NEXT: vaddt.i32 q6, q6, q0
-; CHECK-NEXT: vadd.i32 q0, q6, q7
-; CHECK-NEXT: vaddv.u32 r0, q0
-; CHECK-NEXT: add sp, #32
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vpt.i8 eq, q2, zr
+; CHECK-NEXT: vmlavt.s8 r0, q0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <16 x i8> %b, zeroinitializer
@@ -2095,135 +1807,9 @@ entry:
define arm_aapcs_vfpcc i64 @add_v8i16_v8i32_v8i64_acc_sextzext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i64 %a) {
; CHECK-LABEL: add_v8i16_v8i32_v8i64_acc_sextzext:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r7, lr}
-; CHECK-NEXT: push {r4, r5, r7, lr}
-; CHECK-NEXT: .vsave {d8, d9, d10, d11}
-; CHECK-NEXT: vpush {d8, d9, d10, d11}
-; CHECK-NEXT: vmov.i8 q1, #0x0
-; CHECK-NEXT: vmov.i8 q3, #0xff
-; CHECK-NEXT: vcmp.i16 eq, q2, zr
-; CHECK-NEXT: vpsel q2, q3, q1
-; CHECK-NEXT: vmov.u16 r2, q2[0]
-; CHECK-NEXT: vmov.32 q1[0], r2
-; CHECK-NEXT: vmov.u16 r2, q2[1]
-; CHECK-NEXT: vmov.32 q1[1], r2
-; CHECK-NEXT: vmov.u16 r2, q2[2]
-; CHECK-NEXT: vmov.32 q1[2], r2
-; CHECK-NEXT: vmov.u16 r2, q2[3]
-; CHECK-NEXT: vmov.32 q1[3], r2
-; CHECK-NEXT: vcmp.i32 ne, q1, zr
-; CHECK-NEXT: vmrs r2, p0
-; CHECK-NEXT: and r3, r2, #1
-; CHECK-NEXT: rsbs r3, r3, #0
-; CHECK-NEXT: vmov.32 q4[0], r3
-; CHECK-NEXT: vmov.32 q4[1], r3
-; CHECK-NEXT: ubfx r3, r2, #4, #1
-; CHECK-NEXT: rsbs r3, r3, #0
-; CHECK-NEXT: vmov.32 q4[2], r3
-; CHECK-NEXT: vmov.32 q4[3], r3
-; CHECK-NEXT: vmov.u16 r3, q0[0]
-; CHECK-NEXT: vmov.32 q1[0], r3
-; CHECK-NEXT: vmov.u16 r3, q0[1]
-; CHECK-NEXT: vmov.32 q1[1], r3
-; CHECK-NEXT: vmov.u16 r3, q0[2]
-; CHECK-NEXT: vmov.32 q1[2], r3
-; CHECK-NEXT: vmov.u16 r3, q0[3]
-; CHECK-NEXT: vmov.32 q1[3], r3
-; CHECK-NEXT: vmullb.s16 q3, q1, q1
-; CHECK-NEXT: vmov.i64 q1, #0xffffffff
-; CHECK-NEXT: vmov.f32 s20, s12
-; CHECK-NEXT: vmov.f32 s22, s13
-; CHECK-NEXT: vand q5, q5, q1
-; CHECK-NEXT: vand q4, q5, q4
-; CHECK-NEXT: vmov.f32 s20, s14
-; CHECK-NEXT: vmov r3, s18
-; CHECK-NEXT: vmov r4, s16
-; CHECK-NEXT: vmov r12, s19
-; CHECK-NEXT: vmov lr, s17
-; CHECK-NEXT: vmov.f32 s22, s15
-; CHECK-NEXT: vand q3, q5, q1
-; CHECK-NEXT: adds r5, r4, r3
-; CHECK-NEXT: ubfx r3, r2, #8, #1
-; CHECK-NEXT: rsb.w r3, r3, #0
-; CHECK-NEXT: ubfx r2, r2, #12, #1
-; CHECK-NEXT: vmov.32 q4[0], r3
-; CHECK-NEXT: rsb.w r2, r2, #0
-; CHECK-NEXT: vmov.32 q4[1], r3
-; CHECK-NEXT: adc.w r4, lr, r12
-; CHECK-NEXT: vmov.32 q4[2], r2
-; CHECK-NEXT: vmov.32 q4[3], r2
-; CHECK-NEXT: vand q3, q3, q4
-; CHECK-NEXT: vmov r3, s12
-; CHECK-NEXT: vmov r2, s13
-; CHECK-NEXT: adds r3, r3, r5
-; CHECK-NEXT: vmov r5, s15
-; CHECK-NEXT: adcs r2, r4
-; CHECK-NEXT: vmov r4, s14
-; CHECK-NEXT: adds.w r12, r3, r4
-; CHECK-NEXT: adc.w r3, r2, r5
-; CHECK-NEXT: vmov.u16 r2, q2[4]
-; CHECK-NEXT: vmov.32 q3[0], r2
-; CHECK-NEXT: vmov.u16 r2, q2[5]
-; CHECK-NEXT: vmov.32 q3[1], r2
-; CHECK-NEXT: vmov.u16 r2, q2[6]
-; CHECK-NEXT: vmov.32 q3[2], r2
-; CHECK-NEXT: vmov.u16 r2, q2[7]
-; CHECK-NEXT: vmov.32 q3[3], r2
-; CHECK-NEXT: vcmp.i32 ne, q3, zr
-; CHECK-NEXT: vmrs r2, p0
-; CHECK-NEXT: and r5, r2, #1
-; CHECK-NEXT: rsbs r5, r5, #0
-; CHECK-NEXT: vmov.32 q2[0], r5
-; CHECK-NEXT: vmov.32 q2[1], r5
-; CHECK-NEXT: ubfx r5, r2, #4, #1
-; CHECK-NEXT: rsbs r5, r5, #0
-; CHECK-NEXT: vmov.32 q2[2], r5
-; CHECK-NEXT: vmov.32 q2[3], r5
-; CHECK-NEXT: vmov.u16 r5, q0[4]
-; CHECK-NEXT: vmov.32 q3[0], r5
-; CHECK-NEXT: vmov.u16 r5, q0[5]
-; CHECK-NEXT: vmov.32 q3[1], r5
-; CHECK-NEXT: vmov.u16 r5, q0[6]
-; CHECK-NEXT: vmov.32 q3[2], r5
-; CHECK-NEXT: vmov.u16 r5, q0[7]
-; CHECK-NEXT: vmov.32 q3[3], r5
-; CHECK-NEXT: vmullb.s16 q0, q3, q3
-; CHECK-NEXT: vmov.f32 s12, s0
-; CHECK-NEXT: vmov.f32 s14, s1
-; CHECK-NEXT: vand q3, q3, q1
-; CHECK-NEXT: vand q2, q3, q2
-; CHECK-NEXT: vmov.f32 s12, s2
-; CHECK-NEXT: vmov r4, s8
-; CHECK-NEXT: vmov r5, s9
-; CHECK-NEXT: vmov.f32 s14, s3
-; CHECK-NEXT: vand q0, q3, q1
-; CHECK-NEXT: adds.w r4, r4, r12
-; CHECK-NEXT: adc.w r12, r3, r5
-; CHECK-NEXT: vmov r3, s10
-; CHECK-NEXT: vmov r5, s11
-; CHECK-NEXT: adds r3, r3, r4
-; CHECK-NEXT: ubfx r4, r2, #8, #1
-; CHECK-NEXT: rsb.w r4, r4, #0
-; CHECK-NEXT: ubfx r2, r2, #12, #1
-; CHECK-NEXT: vmov.32 q2[0], r4
-; CHECK-NEXT: rsb.w r2, r2, #0
-; CHECK-NEXT: vmov.32 q2[1], r4
-; CHECK-NEXT: adc.w r5, r5, r12
-; CHECK-NEXT: vmov.32 q2[2], r2
-; CHECK-NEXT: vmov.32 q2[3], r2
-; CHECK-NEXT: vand q0, q0, q2
-; CHECK-NEXT: vmov r4, s0
-; CHECK-NEXT: vmov r2, s1
-; CHECK-NEXT: adds r3, r3, r4
-; CHECK-NEXT: vmov r4, s2
-; CHECK-NEXT: adcs r2, r5
-; CHECK-NEXT: vmov r5, s3
-; CHECK-NEXT: adds r3, r3, r4
-; CHECK-NEXT: adcs r2, r5
-; CHECK-NEXT: adds r0, r0, r3
-; CHECK-NEXT: adcs r1, r2
-; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: pop {r4, r5, r7, pc}
+; CHECK-NEXT: vpt.i16 eq, q2, zr
+; CHECK-NEXT: vmlalvat.s16 r0, r1, q0, q0
+; CHECK-NEXT: bx lr
entry:
%c = icmp eq <8 x i16> %b, zeroinitializer
%xx = sext <8 x i16> %x to <8 x i32>
@@ -2421,174 +2007,8 @@ entry:
define arm_aapcs_vfpcc i32 @add_v16i8_v16i16_v16i32_acc_sextzext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i32 %a) {
; CHECK-LABEL: add_v16i8_v16i16_v16i32_acc_sextzext:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: .pad #32
-; CHECK-NEXT: sub sp, #32
-; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: vcmp.i8 eq, q2, zr
-; CHECK-NEXT: vmov.i8 q2, #0xff
-; CHECK-NEXT: vmov.i8 q0, #0x0
-; CHECK-NEXT: vpsel q1, q2, q0
-; CHECK-NEXT: vmov q3, q2
-; CHECK-NEXT: vmov.u8 r1, q1[0]
-; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill
-; CHECK-NEXT: vmov.16 q2[0], r1
-; CHECK-NEXT: vmov.u8 r1, q1[1]
-; CHECK-NEXT: vmov.16 q2[1], r1
-; CHECK-NEXT: vmov.u8 r1, q1[2]
-; CHECK-NEXT: vmov.16 q2[2], r1
-; CHECK-NEXT: vmov.u8 r1, q1[3]
-; CHECK-NEXT: vmov.16 q2[3], r1
-; CHECK-NEXT: vmov.u8 r1, q1[4]
-; CHECK-NEXT: vmov.16 q2[4], r1
-; CHECK-NEXT: vmov.u8 r1, q1[5]
-; CHECK-NEXT: vmov.16 q2[5], r1
-; CHECK-NEXT: vmov.u8 r1, q1[6]
-; CHECK-NEXT: vmov.16 q2[6], r1
-; CHECK-NEXT: vmov.u8 r1, q1[7]
-; CHECK-NEXT: vmov.16 q2[7], r1
-; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
-; CHECK-NEXT: vcmp.i16 ne, q2, zr
-; CHECK-NEXT: vmov.i32 q6, #0x0
-; CHECK-NEXT: vpsel q5, q3, q0
-; CHECK-NEXT: vmov q7, q6
-; CHECK-NEXT: vmov.u16 r1, q5[4]
-; CHECK-NEXT: vmov.i32 q2, #0xffff
-; CHECK-NEXT: vmov.32 q0[0], r1
-; CHECK-NEXT: vmov.u16 r1, q5[5]
-; CHECK-NEXT: vmov.32 q0[1], r1
-; CHECK-NEXT: vmov.u16 r1, q5[6]
-; CHECK-NEXT: vmov.32 q0[2], r1
-; CHECK-NEXT: vmov.u16 r1, q5[7]
-; CHECK-NEXT: vmov.32 q0[3], r1
-; CHECK-NEXT: vmov.u8 r1, q4[0]
-; CHECK-NEXT: vmov.16 q3[0], r1
-; CHECK-NEXT: vmov.u8 r1, q4[1]
-; CHECK-NEXT: vmov.16 q3[1], r1
-; CHECK-NEXT: vmov.u8 r1, q4[2]
-; CHECK-NEXT: vmov.16 q3[2], r1
-; CHECK-NEXT: vmov.u8 r1, q4[3]
-; CHECK-NEXT: vmov.16 q3[3], r1
-; CHECK-NEXT: vmov.u8 r1, q4[4]
-; CHECK-NEXT: vmov.16 q3[4], r1
-; CHECK-NEXT: vmov.u8 r1, q4[5]
-; CHECK-NEXT: vmov.16 q3[5], r1
-; CHECK-NEXT: vmov.u8 r1, q4[6]
-; CHECK-NEXT: vmov.16 q3[6], r1
-; CHECK-NEXT: vmov.u8 r1, q4[7]
-; CHECK-NEXT: vmov.16 q3[7], r1
-; CHECK-NEXT: vcmp.i32 ne, q0, zr
-; CHECK-NEXT: vmullb.s8 q3, q3, q3
-; CHECK-NEXT: vmov.u16 r1, q3[4]
-; CHECK-NEXT: vmov.32 q0[0], r1
-; CHECK-NEXT: vmov.u16 r1, q3[5]
-; CHECK-NEXT: vmov.32 q0[1], r1
-; CHECK-NEXT: vmov.u16 r1, q3[6]
-; CHECK-NEXT: vmov.32 q0[2], r1
-; CHECK-NEXT: vmov.u16 r1, q3[7]
-; CHECK-NEXT: vmov.32 q0[3], r1
-; CHECK-NEXT: vmov.u8 r1, q1[8]
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vandt q7, q0, q2
-; CHECK-NEXT: vmov.16 q0[0], r1
-; CHECK-NEXT: vmov.u8 r1, q1[9]
-; CHECK-NEXT: vmov.16 q0[1], r1
-; CHECK-NEXT: vmov.u8 r1, q1[10]
-; CHECK-NEXT: vmov.16 q0[2], r1
-; CHECK-NEXT: vmov.u8 r1, q1[11]
-; CHECK-NEXT: vmov.16 q0[3], r1
-; CHECK-NEXT: vmov.u8 r1, q1[12]
-; CHECK-NEXT: vmov.16 q0[4], r1
-; CHECK-NEXT: vmov.u8 r1, q1[13]
-; CHECK-NEXT: vmov.16 q0[5], r1
-; CHECK-NEXT: vmov.u8 r1, q1[14]
-; CHECK-NEXT: vmov.16 q0[6], r1
-; CHECK-NEXT: vmov.u8 r1, q1[15]
-; CHECK-NEXT: vmov.16 q0[7], r1
-; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
-; CHECK-NEXT: vcmp.i16 ne, q0, zr
-; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT: vpsel q0, q1, q0
-; CHECK-NEXT: vmov.u16 r1, q0[4]
-; CHECK-NEXT: vmov.32 q1[0], r1
-; CHECK-NEXT: vmov.u16 r1, q0[5]
-; CHECK-NEXT: vmov.32 q1[1], r1
-; CHECK-NEXT: vmov.u16 r1, q0[6]
-; CHECK-NEXT: vmov.32 q1[2], r1
-; CHECK-NEXT: vmov.u16 r1, q0[7]
-; CHECK-NEXT: vmov.32 q1[3], r1
-; CHECK-NEXT: vmov.u8 r1, q4[8]
-; CHECK-NEXT: vcmp.i32 ne, q1, zr
-; CHECK-NEXT: vmov.16 q1[0], r1
-; CHECK-NEXT: vmov.u8 r1, q4[9]
-; CHECK-NEXT: vmov.16 q1[1], r1
-; CHECK-NEXT: vmov.u8 r1, q4[10]
-; CHECK-NEXT: vmov.16 q1[2], r1
-; CHECK-NEXT: vmov.u8 r1, q4[11]
-; CHECK-NEXT: vmov.16 q1[3], r1
-; CHECK-NEXT: vmov.u8 r1, q4[12]
-; CHECK-NEXT: vmov.16 q1[4], r1
-; CHECK-NEXT: vmov.u8 r1, q4[13]
-; CHECK-NEXT: vmov.16 q1[5], r1
-; CHECK-NEXT: vmov.u8 r1, q4[14]
-; CHECK-NEXT: vmov.16 q1[6], r1
-; CHECK-NEXT: vmov.u8 r1, q4[15]
-; CHECK-NEXT: vmov.16 q1[7], r1
-; CHECK-NEXT: vmullb.s8 q1, q1, q1
-; CHECK-NEXT: vmov.u16 r1, q1[4]
-; CHECK-NEXT: vmov.32 q4[0], r1
-; CHECK-NEXT: vmov.u16 r1, q1[5]
-; CHECK-NEXT: vmov.32 q4[1], r1
-; CHECK-NEXT: vmov.u16 r1, q1[6]
-; CHECK-NEXT: vmov.32 q4[2], r1
-; CHECK-NEXT: vmov.u16 r1, q1[7]
-; CHECK-NEXT: vmov.32 q4[3], r1
-; CHECK-NEXT: vmov.u16 r1, q5[0]
-; CHECK-NEXT: vmovlb.u16 q4, q4
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vaddt.i32 q7, q7, q4
-; CHECK-NEXT: vmov.32 q4[0], r1
-; CHECK-NEXT: vmov.u16 r1, q5[1]
-; CHECK-NEXT: vmov.32 q4[1], r1
-; CHECK-NEXT: vmov.u16 r1, q5[2]
-; CHECK-NEXT: vmov.32 q4[2], r1
-; CHECK-NEXT: vmov.u16 r1, q5[3]
-; CHECK-NEXT: vmov.32 q4[3], r1
-; CHECK-NEXT: vmov.u16 r1, q3[0]
-; CHECK-NEXT: vcmp.i32 ne, q4, zr
-; CHECK-NEXT: vmov.32 q4[0], r1
-; CHECK-NEXT: vmov.u16 r1, q3[1]
-; CHECK-NEXT: vmov.32 q4[1], r1
-; CHECK-NEXT: vmov.u16 r1, q3[2]
-; CHECK-NEXT: vmov.32 q4[2], r1
-; CHECK-NEXT: vmov.u16 r1, q3[3]
-; CHECK-NEXT: vmov.32 q4[3], r1
-; CHECK-NEXT: vmov.u16 r1, q0[0]
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vandt q6, q4, q2
-; CHECK-NEXT: vmov.32 q2[0], r1
-; CHECK-NEXT: vmov.u16 r1, q0[1]
-; CHECK-NEXT: vmov.32 q2[1], r1
-; CHECK-NEXT: vmov.u16 r1, q0[2]
-; CHECK-NEXT: vmov.32 q2[2], r1
-; CHECK-NEXT: vmov.u16 r1, q0[3]
-; CHECK-NEXT: vmov.32 q2[3], r1
-; CHECK-NEXT: vmov.u16 r1, q1[0]
-; CHECK-NEXT: vmov.32 q0[0], r1
-; CHECK-NEXT: vmov.u16 r1, q1[1]
-; CHECK-NEXT: vmov.32 q0[1], r1
-; CHECK-NEXT: vmov.u16 r1, q1[2]
-; CHECK-NEXT: vmov.32 q0[2], r1
-; CHECK-NEXT: vmov.u16 r1, q1[3]
-; CHECK-NEXT: vmov.32 q0[3], r1
-; CHECK-NEXT: vmovlb.u16 q0, q0
-; CHECK-NEXT: vpt.i32 ne, q2, zr
-; CHECK-NEXT: vaddt.i32 q6, q6, q0
-; CHECK-NEXT: vadd.i32 q0, q6, q7
-; CHECK-NEXT: vaddva.u32 r0, q0
-; CHECK-NEXT: add sp, #32
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vpt.i8 eq, q2, zr
+; CHECK-NEXT: vmlavat.s8 r0, q0, q0
; CHECK-NEXT: bx lr
entry:
%c = icmp eq <16 x i8> %b, zeroinitializer
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