[PATCH] D87557: [AArch64][MachineScheduler] Fix operand scheduling for pre/post-increment loads and stores

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 created this revision.
evgeny777 added reviewers: javed.absar, SjoerdMeijer, t.p.northover, kristof.beyls, samparker, flyingforyou.
Herald added subscribers: danielkiss, gbedwell, hiraditya.
Herald added a reviewer: andreadb.
Herald added a project: LLVM.
evgeny777 requested review of this revision.

WriteAdr describes scheduling for first operand of load and last operand of store:

  $x0, $x1, $x2 = LDPXpost $x0, 2          # x0 is first
  STRWpost $wzr, $x0, -4                   # x0 is last


https://reviews.llvm.org/D87557

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/test/CodeGen/AArch64/merge-store-dependency.ll
  llvm/test/tools/llvm-mca/AArch64/Exynos/load.s

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