[llvm] 528554c - [PowerPC] Set the mayRaiseFPException for FCMPUS/FCMPUD

[QingShan Zhang via llvm-commits]

Author: QingShan Zhang
Date: 2020-09-12T02:42:22Z
New Revision: 528554c39b098e2d9a9c7ec51c77717aa07db2a2

URL: https://github.com/llvm/llvm-project/commit/528554c39b098e2d9a9c7ec51c77717aa07db2a2
DIFF: https://github.com/llvm/llvm-project/commit/528554c39b098e2d9a9c7ec51c77717aa07db2a2.diff

LOG: [PowerPC] Set the mayRaiseFPException for FCMPUS/FCMPUD

>From ISA, fcmpu will raise the Floating-Point Invalid Operation
Exception (SNaN) if either of the operands is a Signaling NaN by setting
the bit VXSNAN. But the instruction description didn't set the
mayRaiseFPException which might have impact on the scheduling or some
backend optimization.

Reviewed By: qiucf

Differential Revision: https://reviews.llvm.org/D83937

Added: 
    llvm/test/CodeGen/PowerPC/nofpexcept.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index c865fa10956b..bf7ad639ab6e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2624,7 +2624,7 @@ let isCompare = 1, hasSideEffects = 0 in {
 }
 }
 let PPC970_Unit = 3, Predicates = [HasFPU] in {  // FPU Operations.
-let isCompare = 1, hasSideEffects = 0 in {
+let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in {
   def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
                         "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
   def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),

diff  --git a/llvm/test/CodeGen/PowerPC/nofpexcept.ll b/llvm/test/CodeGen/PowerPC/nofpexcept.ll
new file mode 100644
index 000000000000..e15b06e0babe
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/nofpexcept.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:   -stop-after=finalize-isel -verify-machineinstrs | FileCheck %s 
+
+; Verify if the mayRaiseFPException is set for FCMPD/FCMPS
+define i32 @fcmpu(double %a, double %b) {
+  ; CHECK-LABEL: name: fcmpu
+  ; CHECK: bb.0.entry:
+  ; CHECK:   liveins: $f1, $f2
+  ; CHECK:   [[COPY:%[0-9]+]]:f8rc = COPY $f2
+  ; CHECK:   [[COPY1:%[0-9]+]]:f8rc = COPY $f1
+  ; CHECK:   %2:crrc = nofpexcept FCMPUD [[COPY1]], [[COPY]]
+  ; CHECK:   [[COPY2:%[0-9]+]]:crbitrc = COPY %2.sub_gt
+  ; CHECK:   [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 0
+  ; CHECK:   [[LI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1
+  ; CHECK:   [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[LI8_1]], [[LI8_]], [[COPY2]]
+  ; CHECK:   $x3 = COPY [[ISEL8_]]
+  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
+entry:
+  %r = fcmp ogt double %a, %b
+  %g = zext i1 %r to i32
+  ret i32 %g
+}