[PATCH] D87209: [SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5585
+      SDValue Parity = DAG.getNode(ISD::PARITY, dl, Tmp.getValueType(),
+                                   Tmp.getOperand(0));
+      return DAG.getNode(ISD::TRUNCATE, dl, VT, Parity);
----------------
clang-format doesn't like this


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:28865
+
+  if (Size >= 64) {
+    // Xor the high and low 16-bits together using a 32-bit operation.
----------------
Why ">= 64"?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87209/new/

https://reviews.llvm.org/D87209