[PATCH] D87446: [AMDGPU] Enable scheduling around FP MODE-setting instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SOPInstructions.td:869
+// register, so doesn't have unmodeled side effects.
+def S_SETREG_IMM32_B32_mode : SOPK_Pseudo <
+  "s_setreg_imm32_b32",
----------------
I'm not sure this will be encoded correctly since it's repeating the same instruction definition and not adding the physical aliases. Can you add tests checking the encoding? I think this needs to use PseudoInstExpansion


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87446/new/

https://reviews.llvm.org/D87446