[PATCH] D87542: AMDGPU: Don't sometimes allow instructions before lowered si_end_cf

[Matt Arsenault via Phabricator via llvm-commits]

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Since 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f, this would sometimes
not emit the or to exec at the beginning of the block, where it really
has to be. If there is an instruction that defines one of the source
operands, split the block and turn the si_end_cf into a terminator.

      

This avoids regressions when regalloc fast is switched to inserting
reloads at the beginning of the block, instead of spills at the end of
the block.

      

In a future change, this should always split the block.


https://reviews.llvm.org/D87542

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
  llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
  llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir

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