[PATCH] D87479: [InstCombine] Don't sink the fdiv from (fmul (fdiv 1.0, %x), %y) if the fdiv isn't in the same basic block as the fmul

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

I personally really think this should be viewed as phase ordering issue, that should be addressed by adding/moving pases in pipeline.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87479/new/

https://reviews.llvm.org/D87479