[PATCH] D87232: [SVE][CodeGen] Lower floating point -> integer conversions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.h:84
+  FP_TO_UINT_MERGE_PASSTHRU,
+  FP_TO_SINT_MERGE_PASSTHRU,
   FSUB_PRED,
----------------
efriedma wrote:
> Probably should be named FP_TO_UINT_SAT_MERGE_PASSTHRU or something like that, if you're going to use it to lower llvm.aarch64.sve.fcvtzu.  (See D54749)
I had a feeling you might say this.  The problem is this is more than a rename because the SAT nodes take an additional parameter.  This is not really a hurdle but there's a question as to where you draw the line.  All the intrinsics expect to produce results that match the instructions on which they're based.  This would suggest we can never use names based on similar ISD nodes because the common nodes do not define all corner cases.  This seems like overkill considering the _PRED/_MERGE nodes are all under the AArch64ISD namespace, which to me suggests they follow AArch64 semantics.


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  https://reviews.llvm.org/D87232/new/

https://reviews.llvm.org/D87232