[llvm] 5692497 - [gn build] (semi-manually) port 009cd4e4910

[Nico Weber via llvm-commits]

Author: Nico Weber
Date: 2020-09-10T15:15:59-04:00
New Revision: 5692497aef08ab4810f125669bc2f6aa79d9ec7e

URL: https://github.com/llvm/llvm-project/commit/5692497aef08ab4810f125669bc2f6aa79d9ec7e
DIFF: https://github.com/llvm/llvm-project/commit/5692497aef08ab4810f125669bc2f6aa79d9ec7e.diff

LOG: [gn build] (semi-manually) port 009cd4e4910

Added: 
    

Modified: 
    llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn

Removed: 
    


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diff  --git a/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
index 3a452fc6e060..9adb514705d4 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
@@ -18,17 +18,32 @@ tablegen("PPCGenFastISel") {
   td_file = "PPC.td"
 }
 
+tablegen("PPCGenGlobalISel") {
+  visibility = [ ":LLVMPowerPCCodeGen" ]
+  args = [ "-gen-global-isel" ]
+  td_file = "PPC.td"
+}
+
+tablegen("PPCGenRegisterBank") {
+  visibility = [ ":LLVMPowerPCCodeGen" ]
+  args = [ "-gen-register-bank" ]
+  td_file = "PPC.td"
+}
+
 static_library("LLVMPowerPCCodeGen") {
   deps = [
     ":PPCGenCallingConv",
     ":PPCGenDAGISel",
     ":PPCGenFastISel",
+    ":PPCGenGlobalISel",
+    ":PPCGenRegisterBank",
     "MCTargetDesc",
     "TargetInfo",
     "//llvm/include/llvm/Config:llvm-config",
     "//llvm/lib/Analysis",
     "//llvm/lib/CodeGen",
     "//llvm/lib/CodeGen/AsmPrinter",
+    "//llvm/lib/CodeGen/GlobalISel",
     "//llvm/lib/CodeGen/SelectionDAG",
     "//llvm/lib/IR",
     "//llvm/lib/MC",
@@ -38,6 +53,10 @@ static_library("LLVMPowerPCCodeGen") {
   ]
   include_dirs = [ "." ]
   sources = [
+    "GISel/PPCCallLowering.cpp",
+    "GISel/PPCInstructionSelector.cpp",
+    "GISel/PPCLegalizerInfo.cpp",
+    "GISel/PPCRegisterBankInfo.cpp",
     "PPCAsmPrinter.cpp",
     "PPCBoolRetToInt.cpp",
     "PPCBranchCoalescing.cpp",