[PATCH] D81172: [AMDGPU] Implement hardware bug workaround for image instructions

[Rodrigo Dominguez via Phabricator via llvm-commits]

rdomingu added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3411-3415
+      auto Unmerge = B.buildUnmerge(S16, Reg);
+      for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
+        PackedRegs.push_back(Unmerge.getReg(I));
+      PackedRegs.resize(8, B.buildUndef(S16).getReg(0));
+      Reg = B.buildBuildVector(LLT::vector(8, S16), PackedRegs).getReg(0);
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arsenm wrote:
> It would be preferable to emit a concat_vectors of <2 x s16> pieces here
Sorry, I'm new to this. Why would concat_vectors be preferable than build_vector? Could you please elaborate?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81172/new/

https://reviews.llvm.org/D81172