[PATCH] D86078: [AArch64] Improved lowering for saturating float to int.

[Bevin Hansson via Phabricator via llvm-commits]

ebevhan added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll:175
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    ret
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efriedma wrote:
> This should probably just be "fcvtzs v0.2d, v0.2d; sqxtn v0.2s, v0.2d".
Is sqxtn ever selected without intrinsics? I would assume that a simple minmax and trunc pattern would catch it, but that doesn't happen.


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  https://reviews.llvm.org/D86078/new/

https://reviews.llvm.org/D86078