[PATCH] D46884: [AArch64] Cortex-A55 scheduler model

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added inline comments.
Herald added a subscriber: danielkiss.


================
Comment at: lib/Target/AArch64/AArch64SchedA55.td:160
+                                                     let ResourceCycles = [14]; }
+def CortexA55WriteFDivDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 33;
+                                                     let ResourceCycles = [29]; }
----------------
@SjoerdMeijer Latency/hazard for FDivDP seem to not match those in optimization guide for Cortex-A55 (should be 22/19). Why's that? There are mismatches in other places also (for instance WriteLD should (?) be 3 cycles, not 4)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D46884/new/

https://reviews.llvm.org/D46884