[PATCH] D87348: [ARM] Tail predicate VQDMULH and VQRDMULH
Sam Parker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 10 00:20:37 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1919b6505232: [ARM] Tail predicate VQDMULH and VQRDMULH (authored by samparker).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D87348/new/
https://reviews.llvm.org/D87348
Files:
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
llvm/unittests/Target/ARM/MachineInstrTest.cpp
Index: llvm/unittests/Target/ARM/MachineInstrTest.cpp
===================================================================
--- llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -754,6 +754,12 @@
case MVE_VQADDu16:
case MVE_VQADDu32:
case MVE_VQADDu8:
+ case MVE_VQDMULH_qr_s16:
+ case MVE_VQDMULH_qr_s32:
+ case MVE_VQDMULH_qr_s8:
+ case MVE_VQDMULHi16:
+ case MVE_VQDMULHi32:
+ case MVE_VQDMULHi8:
case MVE_VQDMULL_qr_s16bh:
case MVE_VQDMULL_qr_s16th:
case MVE_VQDMULL_qr_s32bh:
@@ -762,6 +768,12 @@
case MVE_VQDMULLs16th:
case MVE_VQDMULLs32bh:
case MVE_VQDMULLs32th:
+ case MVE_VQRDMULH_qr_s16:
+ case MVE_VQRDMULH_qr_s32:
+ case MVE_VQRDMULH_qr_s8:
+ case MVE_VQRDMULHi16:
+ case MVE_VQRDMULHi32:
+ case MVE_VQRDMULHi8:
case MVE_VQNEGs16:
case MVE_VQNEGs32:
case MVE_VQNEGs8:
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
@@ -7,23 +7,13 @@
; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: ldrd r5, r12, [sp, #80]
-; CHECK-NEXT: cmp.w r12, #4
-; CHECK-NEXT: mov r4, r12
; CHECK-NEXT: vmvn.i32 q0, #0x80000000
-; CHECK-NEXT: it ge
-; CHECK-NEXT: movge r4, #4
; CHECK-NEXT: vmov.i32 q1, #0x3f
-; CHECK-NEXT: sub.w r4, r12, r4
; CHECK-NEXT: vmov.i32 q2, #0x1
-; CHECK-NEXT: add.w lr, r4, #3
-; CHECK-NEXT: movs r4, #1
-; CHECK-NEXT: add.w lr, r4, lr, lsr #2
-; CHECK-NEXT: dls lr, lr
+; CHECK-NEXT: dlstp.32 lr, r12
; CHECK-NEXT: .LBB0_1: @ %bb6
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vctp.32 r12
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vldrwt.u32 q4, [r1], #16
+; CHECK-NEXT: vldrw.u32 q4, [r1], #16
; CHECK-NEXT: vabs.s32 q5, q4
; CHECK-NEXT: vcls.s32 q3, q5
; CHECK-NEXT: vshl.u32 q5, q5, q3
@@ -41,15 +31,13 @@
; CHECK-NEXT: vqshl.s32 q5, q5, #1
; CHECK-NEXT: vpt.s32 lt, q4, zr
; CHECK-NEXT: vnegt.s32 q5, q5
-; CHECK-NEXT: vctp.32 r12
-; CHECK-NEXT: sub.w r12, r12, #4
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrwt.u32 q4, [r0], #16
; CHECK-NEXT: vqrdmulh.s32 q4, q4, q5
; CHECK-NEXT: vpstt
; CHECK-NEXT: vstrwt.32 q4, [r2], #16
; CHECK-NEXT: vstrwt.32 q3, [r3], #16
-; CHECK-NEXT: le lr, .LBB0_1
+; CHECK-NEXT: letp lr, .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %bb44
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5, r7, pc}
Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -1918,6 +1918,7 @@
let Inst{12-8} = 0b01011;
let Inst{4} = 0b0;
let Inst{0} = 0b0;
+ let validForTailPredication = 1;
}
multiclass MVE_VQxDMULH_m<string iname, MVEVectorVTInfo VTI,
@@ -5453,6 +5454,7 @@
let Inst{12} = 0b0;
let Inst{8} = 0b0;
let Inst{5} = 0b1;
+ let validForTailPredication = 1;
}
multiclass MVE_VxxMUL_qr_m<string iname, MVEVectorVTInfo VTI, bit bit_28,
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