[PATCH] D87222: [PowerPC] [FPEnv] Disable strict FP mutation by default for PowerPC

[Qiu Chaofan via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6afb27910044: [PowerPC] [FPEnv] Disable strict FP mutation by default (authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87222/new/

https://reviews.llvm.org/D87222

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll


Index: llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
@@ -7168,19 +7168,19 @@
 ; PC64LE-NEXT:    addis 3, 2, .LCPI133_0 at toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI133_1 at toc@ha
 ; PC64LE-NEXT:    addis 5, 2, .LCPI133_2 at toc@ha
-; PC64LE-NEXT:    lfs 1, .LCPI133_0 at toc@l(3)
+; PC64LE-NEXT:    lfs 3, .LCPI133_0 at toc@l(3)
 ; PC64LE-NEXT:    lfs 2, .LCPI133_1 at toc@l(4)
-; PC64LE-NEXT:    lfs 3, .LCPI133_2 at toc@l(5)
+; PC64LE-NEXT:    lfs 1, .LCPI133_2 at toc@l(5)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fpext_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_0 at toc@ha
-; PC64LE9-NEXT:    lfs 1, .LCPI133_0 at toc@l(3)
+; PC64LE9-NEXT:    lfs 3, .LCPI133_0 at toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_1 at toc@ha
 ; PC64LE9-NEXT:    lfs 2, .LCPI133_1 at toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_2 at toc@ha
-; PC64LE9-NEXT:    lfs 3, .LCPI133_2 at toc@l(3)
+; PC64LE9-NEXT:    lfs 1, .LCPI133_2 at toc@l(3)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3477,7 +3477,7 @@
 def : Pat<(f64 (extloadf32 xaddr:$src)),
           (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
 
-def : Pat<(f64 (fpextend f32:$src)),
+def : Pat<(f64 (any_fpextend f32:$src)),
           (COPY_TO_REGCLASS $src, F8RC)>;
 }
 
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1320,6 +1320,8 @@
     MaxLoadsPerMemcmpOptSize = 4;
   }
 
+  IsStrictFPEnabled = true;
+
   // Let the subtarget (CPU) decide if a predictable select is more expensive
   // than the corresponding branch. This information is used in CGP to decide
   // when to convert selects into branches.


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