[llvm] 6afb279 - [PowerPC] [FPEnv] Disable strict FP mutation by default

[Qiu Chaofan via llvm-commits]

Author: Qiu Chaofan
Date: 2020-09-10T13:28:09+08:00
New Revision: 6afb27910044cc0906b99b1284fbd29208816f82

URL: https://github.com/llvm/llvm-project/commit/6afb27910044cc0906b99b1284fbd29208816f82
DIFF: https://github.com/llvm/llvm-project/commit/6afb27910044cc0906b99b1284fbd29208816f82.diff

LOG: [PowerPC] [FPEnv] Disable strict FP mutation by default

22a0edd0 introduced a config IsStrictFPEnabled, which controls the
strict floating point mutation (transforming some strict-fp operations
into non-strict in ISel). This patch disables the mutation by default
since we've finished PowerPC strict-fp enablement in backend.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D87222

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index fc9a80919fc1..469fe9701d06 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1320,6 +1320,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
     MaxLoadsPerMemcmpOptSize = 4;
   }
 
+  IsStrictFPEnabled = true;
+
   // Let the subtarget (CPU) decide if a predictable select is more expensive
   // than the corresponding branch. This information is used in CGP to decide
   // when to convert selects into branches.

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index a6932005d5ad..c865fa10956b 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3477,7 +3477,7 @@ def : Pat<(f64 (extloadf32 iaddr:$src)),
 def : Pat<(f64 (extloadf32 xaddr:$src)),
           (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
 
-def : Pat<(f64 (fpextend f32:$src)),
+def : Pat<(f64 (any_fpextend f32:$src)),
           (COPY_TO_REGCLASS $src, F8RC)>;
 }
 

diff  --git a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
index 7345d65be14a..21fc855aa854 100644
--- a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
@@ -7168,19 +7168,19 @@ define <3 x double> @constrained_vector_fpext_v3f32() #0 {
 ; PC64LE-NEXT:    addis 3, 2, .LCPI133_0 at toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI133_1 at toc@ha
 ; PC64LE-NEXT:    addis 5, 2, .LCPI133_2 at toc@ha
-; PC64LE-NEXT:    lfs 1, .LCPI133_0 at toc@l(3)
+; PC64LE-NEXT:    lfs 3, .LCPI133_0 at toc@l(3)
 ; PC64LE-NEXT:    lfs 2, .LCPI133_1 at toc@l(4)
-; PC64LE-NEXT:    lfs 3, .LCPI133_2 at toc@l(5)
+; PC64LE-NEXT:    lfs 1, .LCPI133_2 at toc@l(5)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fpext_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_0 at toc@ha
-; PC64LE9-NEXT:    lfs 1, .LCPI133_0 at toc@l(3)
+; PC64LE9-NEXT:    lfs 3, .LCPI133_0 at toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_1 at toc@ha
 ; PC64LE9-NEXT:    lfs 2, .LCPI133_1 at toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_2 at toc@ha
-; PC64LE9-NEXT:    lfs 3, .LCPI133_2 at toc@l(3)
+; PC64LE9-NEXT:    lfs 1, .LCPI133_2 at toc@l(3)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(