[PATCH] D87416: [SLPVectorizer][X86][AMDGPU] Remove fcmp+select to fmin/fmax reduction support.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, nikic, arsenm, efriedma, vdmitrie.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
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craig.topper requested review of this revision.
Herald added a subscriber: wdng.

Previously we could match fcmp+select to a reduction if the fcmp had
the nonans fast math flag. But if the select had the nonans fast
math flag, InstCombine would turn it into a fminnum/fmaxnum intrinsic
before SLP gets to it. Seems fairly likely that if one of the
fcmp+select pair have the fast math flag, they both would.

My plan is to start vectorizing the fmaxnum/fminnum version soon,
but I wanted to get this code out as it had some of the strangest
fast math flag behaviors.


https://reviews.llvm.org/D87416

Files:
  llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
  llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
  llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
  llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
  llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll

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