[PATCH] D86147: [LangRef] Revise semantics of get.active.lane.mask

[Luke Kenneth Casson Leighton via Phabricator via llvm-commits]

lkcl added a comment.

In D86147#2258555 <https://reviews.llvm.org/D86147#2258555>, @SjoerdMeijer wrote:

> Hi Luke, thanks for sharing your thoughts. I agree with your analysis. The in-tree vector extension that I am aware of that supports first faulting loads is Arm's SVE. While I work on Arm's MVE, I hope and think this is useful for SVE (and other targets) too, i.e. I think  ffirst mask capability can be used. But since the devil is in the details here, an implementation would need to prove this. Hopefully that happens soon.

:)

i am aware that RVV has fail-on-first, and we are adding it to SimpleV as well.

SV will also have _data_ dependent fail-on-first and given that we are extending PowerISA this will likely be done through vectorisation of Condition Registers.

i.e. if a particular CR bit (which is set based on the result  of the instruction is zero, +ve or -ve) is set this is taken to be the "fail" of "fail on first".

it means that ffirst and masking applies to data rather than just LD/STs.

one thing to watch out for and definitely clarify: is the mask set on *all* elements?

ffirst very specifically modifies the Vector Length and this is radically different from plain predicate masking.

predicate masking masks any elements anywhere in the vector but does not modify the vector length.


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