[PATCH] D77804: [DAG] Enable ISD::SHL/SRL SimplifyMultipleUseDemandedBits handling (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 290750.
RKSimon added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77804/new/

https://reviews.llvm.org/D77804

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/bswap.ll
  llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/test/CodeGen/AMDGPU/saddsat.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/trunc-combine.ll
  llvm/test/CodeGen/AMDGPU/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/usubsat.ll
  llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/ARM/ror.ll
  llvm/test/CodeGen/ARM/uxtb.ll
  llvm/test/CodeGen/RISCV/rv64Zbb.ll
  llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
  llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
  llvm/test/CodeGen/X86/ctpop-combine.ll
  llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/X86/ins_subreg_coalesce-1.ll
  llvm/test/CodeGen/X86/load-local-v3i129.ll
  llvm/test/CodeGen/X86/load-local-v4i5.ll
  llvm/test/CodeGen/X86/masked_compressstore.ll
  llvm/test/CodeGen/X86/mul128.ll
  llvm/test/CodeGen/X86/shift-mask.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll
  llvm/test/CodeGen/X86/vector-mulfix-legalize.ll

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