[llvm] 95b7040 - [AMDGPU][MC] Improved diagnostic messages for invalid registers
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 06:44:29 PDT 2020
Author: Dmitry Preobrazhensky
Date: 2020-09-09T16:44:03+03:00
New Revision: 95b7040e43841802e1ccba59b46e7773c47c4ad6
URL: https://github.com/llvm/llvm-project/commit/95b7040e43841802e1ccba59b46e7773c47c4ad6
DIFF: https://github.com/llvm/llvm-project/commit/95b7040e43841802e1ccba59b46e7773c47c4ad6.diff
LOG: [AMDGPU][MC] Improved diagnostic messages for invalid registers
Corrected parser to issue meaningful error messages for invalid and malformed registers.
See bug 41303: https://bugs.llvm.org/show_bug.cgi?id=41303
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D87234
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/test/MC/AMDGPU/expressions.s
llvm/test/MC/AMDGPU/flat-scratch.s
llvm/test/MC/AMDGPU/literals.s
llvm/test/MC/AMDGPU/mtbuf.s
llvm/test/MC/AMDGPU/out-of-range-registers.s
llvm/test/MC/AMDGPU/reg-syntax-err.s
llvm/test/MC/AMDGPU/reg-syntax-extra.s
llvm/test/MC/AMDGPU/smem.s
llvm/test/MC/AMDGPU/smrd-err.s
llvm/test/MC/AMDGPU/smrd.s
llvm/test/MC/AMDGPU/sop1-err.s
llvm/test/MC/AMDGPU/sop1.s
llvm/test/MC/AMDGPU/sop2.s
llvm/test/MC/AMDGPU/sopk.s
llvm/test/MC/AMDGPU/trap.s
llvm/test/MC/AMDGPU/vop3.s
llvm/test/MC/AMDGPU/vop_sdwa.s
llvm/test/MC/AMDGPU/xnack-mask.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index db74f8a54c0a..d2eb7c1726e2 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1070,7 +1070,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
std::string &CollectString);
bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
- RegisterKind RegKind, unsigned Reg1);
+ RegisterKind RegKind, unsigned Reg1, SMLoc Loc);
bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
unsigned &RegNum, unsigned &RegWidth,
bool RestoreOnFailure = false);
@@ -1088,7 +1088,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool ParseRegRange(unsigned& Num, unsigned& Width);
unsigned getRegularReg(RegisterKind RegKind,
unsigned RegNum,
- unsigned RegWidth);
+ unsigned RegWidth,
+ SMLoc Loc);
bool isRegister();
bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const;
@@ -2065,7 +2066,8 @@ OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(unsigned &RegNo,
}
bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
- RegisterKind RegKind, unsigned Reg1) {
+ RegisterKind RegKind, unsigned Reg1,
+ SMLoc Loc) {
switch (RegKind) {
case IS_SPECIAL:
if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {
@@ -2098,12 +2100,14 @@ bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
RegWidth = 2;
return true;
}
+ Error(Loc, "register does not fit in the list");
return false;
case IS_VGPR:
case IS_SGPR:
case IS_AGPR:
case IS_TTMP:
if (Reg1 != Reg + RegWidth) {
+ Error(Loc, "registers in a list must have consecutive indices");
return false;
}
RegWidth++;
@@ -2186,7 +2190,8 @@ AMDGPUAsmParser::isRegister()
unsigned
AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,
unsigned RegNum,
- unsigned RegWidth) {
+ unsigned RegWidth,
+ SMLoc Loc) {
assert(isRegularReg(RegKind));
@@ -2197,18 +2202,24 @@ AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,
AlignSize = std::min(RegWidth, 4u);
}
- if (RegNum % AlignSize != 0)
+ if (RegNum % AlignSize != 0) {
+ Error(Loc, "invalid register alignment");
return AMDGPU::NoRegister;
+ }
unsigned RegIdx = RegNum / AlignSize;
int RCID = getRegClass(RegKind, RegWidth);
- if (RCID == -1)
+ if (RCID == -1) {
+ Error(Loc, "invalid or unsupported register size");
return AMDGPU::NoRegister;
+ }
const MCRegisterInfo *TRI = getContext().getRegisterInfo();
const MCRegisterClass RC = TRI->getRegClass(RCID);
- if (RegIdx >= RC.getNumRegs())
+ if (RegIdx >= RC.getNumRegs()) {
+ Error(Loc, "register index is out of range");
return AMDGPU::NoRegister;
+ }
return RC.getRegister(RegIdx);
}
@@ -2216,24 +2227,40 @@ AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,
bool
AMDGPUAsmParser::ParseRegRange(unsigned& Num, unsigned& Width) {
int64_t RegLo, RegHi;
- if (!trySkipToken(AsmToken::LBrac))
+ if (!skipToken(AsmToken::LBrac, "missing register index"))
return false;
+ SMLoc FirstIdxLoc = getLoc();
+ SMLoc SecondIdxLoc;
+
if (!parseExpr(RegLo))
return false;
if (trySkipToken(AsmToken::Colon)) {
+ SecondIdxLoc = getLoc();
if (!parseExpr(RegHi))
return false;
} else {
RegHi = RegLo;
}
- if (!trySkipToken(AsmToken::RBrac))
+ if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
+ return false;
+
+ if (!isUInt<32>(RegLo)) {
+ Error(FirstIdxLoc, "invalid register index");
+ return false;
+ }
+
+ if (!isUInt<32>(RegHi)) {
+ Error(SecondIdxLoc, "invalid register index");
return false;
+ }
- if (!isUInt<32>(RegLo) || !isUInt<32>(RegHi) || RegLo > RegHi)
+ if (RegLo > RegHi) {
+ Error(FirstIdxLoc, "first register index should not exceed second index");
return false;
+ }
Num = static_cast<unsigned>(RegLo);
Width = (RegHi - RegLo) + 1;
@@ -2260,10 +2287,14 @@ unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
SmallVectorImpl<AsmToken> &Tokens) {
assert(isToken(AsmToken::Identifier));
StringRef RegName = getTokenStr();
+ auto Loc = getLoc();
const RegInfo *RI = getRegularRegInfo(RegName);
- if (!RI)
+ if (!RI) {
+ Error(Loc, "invalid register name");
return AMDGPU::NoRegister;
+ }
+
Tokens.push_back(getToken());
lex(); // skip register name
@@ -2271,8 +2302,10 @@ unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
StringRef RegSuffix = RegName.substr(RI->Name.size());
if (!RegSuffix.empty()) {
// Single 32-bit register: vXX.
- if (!getRegNum(RegSuffix, RegNum))
+ if (!getRegNum(RegSuffix, RegNum)) {
+ Error(Loc, "invalid register index");
return AMDGPU::NoRegister;
+ }
RegWidth = 1;
} else {
// Range of registers: v[XX:YY]. ":YY" is optional.
@@ -2280,44 +2313,59 @@ unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
return AMDGPU::NoRegister;
}
- return getRegularReg(RegKind, RegNum, RegWidth);
+ return getRegularReg(RegKind, RegNum, RegWidth, Loc);
}
unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
unsigned &RegWidth,
SmallVectorImpl<AsmToken> &Tokens) {
unsigned Reg = AMDGPU::NoRegister;
+ auto ListLoc = getLoc();
- if (!trySkipToken(AsmToken::LBrac))
+ if (!skipToken(AsmToken::LBrac,
+ "expected a register or a list of registers")) {
return AMDGPU::NoRegister;
+ }
// List of consecutive registers, e.g.: [s0,s1,s2,s3]
+ auto Loc = getLoc();
if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))
return AMDGPU::NoRegister;
- if (RegWidth != 1)
+ if (RegWidth != 1) {
+ Error(Loc, "expected a single 32-bit register");
return AMDGPU::NoRegister;
+ }
for (; trySkipToken(AsmToken::Comma); ) {
RegisterKind NextRegKind;
unsigned NextReg, NextRegNum, NextRegWidth;
+ Loc = getLoc();
- if (!ParseAMDGPURegister(NextRegKind, NextReg, NextRegNum, NextRegWidth,
- Tokens))
+ if (!ParseAMDGPURegister(NextRegKind, NextReg,
+ NextRegNum, NextRegWidth,
+ Tokens)) {
return AMDGPU::NoRegister;
- if (NextRegWidth != 1)
+ }
+ if (NextRegWidth != 1) {
+ Error(Loc, "expected a single 32-bit register");
return AMDGPU::NoRegister;
- if (NextRegKind != RegKind)
+ }
+ if (NextRegKind != RegKind) {
+ Error(Loc, "registers in a list must be of the same kind");
return AMDGPU::NoRegister;
- if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg))
+ }
+ if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))
return AMDGPU::NoRegister;
}
- if (!trySkipToken(AsmToken::RBrac))
+ if (!skipToken(AsmToken::RBrac,
+ "expected a comma or a closing square bracket")) {
return AMDGPU::NoRegister;
+ }
if (isRegularReg(RegKind))
- Reg = getRegularReg(RegKind, RegNum, RegWidth);
+ Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc);
return Reg;
}
@@ -2325,6 +2373,7 @@ unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
unsigned &RegNum, unsigned &RegWidth,
SmallVectorImpl<AsmToken> &Tokens) {
+ auto Loc = getLoc();
Reg = AMDGPU::NoRegister;
if (isToken(AsmToken::Identifier)) {
@@ -2336,12 +2385,26 @@ bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
}
const MCRegisterInfo *TRI = getContext().getRegisterInfo();
- return Reg != AMDGPU::NoRegister && subtargetHasRegister(*TRI, Reg);
+ if (Reg == AMDGPU::NoRegister) {
+ assert(Parser.hasPendingError());
+ return false;
+ }
+
+ if (!subtargetHasRegister(*TRI, Reg)) {
+ if (Reg == AMDGPU::SGPR_NULL) {
+ Error(Loc, "'null' operand is not supported on this GPU");
+ } else {
+ Error(Loc, "register not available on this GPU");
+ }
+ return false;
+ }
+
+ return true;
}
bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
unsigned &RegNum, unsigned &RegWidth,
- bool RestoreOnFailure) {
+ bool RestoreOnFailure /*=false*/) {
Reg = AMDGPU::NoRegister;
SmallVector<AsmToken, 1> Tokens;
@@ -2413,8 +2476,6 @@ AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
unsigned Reg, RegNum, RegWidth;
if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {
- //FIXME: improve error messages (bug 41303).
- Error(StartLoc, "not a valid operand.");
return nullptr;
}
if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) {
diff --git a/llvm/test/MC/AMDGPU/expressions.s b/llvm/test/MC/AMDGPU/expressions.s
index 57f47d8f0345..0b7bdcdebb88 100644
--- a/llvm/test/MC/AMDGPU/expressions.s
+++ b/llvm/test/MC/AMDGPU/expressions.s
@@ -327,8 +327,8 @@ v_sin_f32 v0, -[ttmp0]
s1000=1
v_sin_f32 v0, -s1000
-// NOVI: error: not a valid operand.
+// NOVI: error: register index is out of range
xnack_mask_lo=1
v_sin_f32 v0, xnack_mask_lo
-// NOVI: error: not a valid operand.
+// NOVI: error: register not available on this GPU
diff --git a/llvm/test/MC/AMDGPU/flat-scratch.s b/llvm/test/MC/AMDGPU/flat-scratch.s
index eea2f0d07f3e..9ff9ee3af7e5 100644
--- a/llvm/test/MC/AMDGPU/flat-scratch.s
+++ b/llvm/test/MC/AMDGPU/flat-scratch.s
@@ -5,32 +5,32 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
s_mov_b64 flat_scratch, -1
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
// CI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x04,0xe8,0xbe]
// VI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x01,0xe6,0xbe]
s_mov_b32 flat_scratch_lo, -1
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
// CI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x03,0xe8,0xbe]
// VI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x00,0xe6,0xbe]
s_mov_b32 flat_scratch_hi, -1
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
// CI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x03,0xe9,0xbe]
// VI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x00,0xe7,0xbe]
s_mov_b64 flat_scratch_lo, -1
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
// NOCI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
s_mov_b64 flat_scratch_hi, -1
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
// NOCI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
s_mov_b32 flat_scratch, -1
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
// NOCI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s
index b666b7d1cb78..ce6893ed057b 100644
--- a/llvm/test/MC/AMDGPU/literals.s
+++ b/llvm/test/MC/AMDGPU/literals.s
@@ -640,11 +640,11 @@ v_ceil_f32_sdwa v5, |execz| dst_sel:DWORD src0_sel:DWORD
// named inline values: shared_base, shared_limit, private_base, etc
//---------------------------------------------------------------------------//
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: buffer_atomic_add v0, off, s[0:3], src_shared_base offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xeb]
buffer_atomic_add v0, off, s[0:3], src_shared_base offset:4095
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_i32 s0, src_shared_base, s0 ; encoding: [0xeb,0x00,0x00,0x81]
s_add_i32 s0, src_shared_base, s0
@@ -654,119 +654,127 @@ s_add_i32 s0, src_shared_base, s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_i32 s0, src_shared_limit, s0 ; encoding: [0xec,0x00,0x00,0x81]
s_add_i32 s0, src_shared_limit, s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81]
s_add_i32 s0, src_private_base, s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81]
s_add_i32 s0, src_private_limit, s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_i32 s0, src_pops_exiting_wave_id, s0 ; encoding: [0xef,0x00,0x00,0x81]
s_add_i32 s0, src_pops_exiting_wave_id, s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_shared_base ; encoding: [0x00,0xeb,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_shared_base
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_shared_limit ; encoding: [0x00,0xec,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_shared_limit
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_private_base
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_private_limit
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id ; encoding: [0x00,0xef,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_add_u16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x4c]
v_add_u16 v0, src_shared_base, v0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_add_u16_sdwa v0, src_shared_base, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x4c,0xeb,0x06,0x86,0x06]
v_add_u16_sdwa v0, src_shared_base, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_add_u16_sdwa v0, v0, src_shared_base dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xd6,0x01,0x4c,0x00,0x06,0x06,0x86]
v_add_u16_sdwa v0, v0, src_shared_base dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_add_u32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x68]
v_add_u32 v0, src_shared_base, v0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_add_u32_e64 v0, src_shared_base, v0 ; encoding: [0x00,0x00,0x34,0xd1,0xeb,0x00,0x02,0x00]
v_add_u32_e64 v0, src_shared_base, v0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_cmp_eq_i64_e32 vcc, src_shared_base, v[0:1] ; encoding: [0xeb,0x00,0xc4,0x7d]
v_cmp_eq_i64 vcc, src_shared_base, v[0:1]
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_max_f16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x5a]
v_max_f16 v0, src_shared_base, v0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_max_f32_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x16]
v_max_f32 v0, src_shared_base, v0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_max_f64 v[0:1], src_shared_base, v[0:1] ; encoding: [0x00,0x00,0x83,0xd2,0xeb,0x00,0x02,0x00]
v_max_f64 v[0:1], src_shared_base, v[0:1]
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_pk_add_f16 v0, src_shared_base, v0 ; encoding: [0x00,0x00,0x8f,0xd3,0xeb,0x00,0x02,0x18]
v_pk_add_f16 v0, src_shared_base, v0
-// NOSICIVI: error: not a valid operand
// GFX9: v_ceil_f16_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0x85,0xd1,0xeb,0x00,0x00,0x20]
+// NOSICI: error: not a valid operand.
+// NOVI: error: register not available on this GPU
v_ceil_f16 v0, neg(src_shared_base)
-// NOSICIVI: error: not a valid operand
// GFX9: v_ceil_f16_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0x85,0xd1,0xeb,0x00,0x00,0x00]
+// NOSICI: error: not a valid operand.
+// NOVI: error: register not available on this GPU
v_ceil_f16 v0, abs(src_shared_base)
-// NOSICIVI: error: not a valid operand
// GFX9: v_ceil_f64_e64 v[5:6], |src_shared_base| ; encoding: [0x05,0x01,0x58,0xd1,0xeb,0x00,0x00,0x00]
+// NOSI: error: not a valid operand.
+// NOCIVI: error: register not available on this GPU
+// NOVI: error: register not available on this GPU
v_ceil_f64 v[5:6], |src_shared_base|
-// NOSICIVI: error: not a valid operand
// GFX9: v_ceil_f64_e64 v[5:6], -src_shared_base ; encoding: [0x05,0x00,0x58,0xd1,0xeb,0x00,0x00,0x20]
+// NOSI: error: not a valid operand.
+// NOCIVI: error: register not available on this GPU
+// NOVI: error: register not available on this GPU
v_ceil_f64 v[5:6], -src_shared_base
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_ceil_f32_e64 v0, -src_shared_base ; encoding: [0x00,0x00,0x5d,0xd1,0xeb,0x00,0x00,0x20]
v_ceil_f32 v0, -src_shared_base
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_ceil_f32_e64 v0, |src_shared_base| ; encoding: [0x00,0x01,0x5d,0xd1,0xeb,0x00,0x00,0x00]
v_ceil_f32 v0, |src_shared_base|
-// NOSICIVI: error: not a valid operand
// GFX9: v_ceil_f16_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xeb,0x16,0xa6,0x00]
+// NOSICI: error: not a valid operand.
+// NOVI: error: register not available on this GPU
v_ceil_f16_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE
-// NOSICIVI: error: not a valid operand
// GFX9: v_ceil_f16_sdwa v5, -src_shared_base dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xeb,0x16,0x96,0x00]
+// NOSICI: error: not a valid operand.
+// NOVI: error: register not available on this GPU
v_ceil_f16_sdwa v5, -src_shared_base dst_sel:DWORD dst_unused:UNUSED_PRESERVE
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_ceil_f32_sdwa v5, src_shared_base dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xeb,0x16,0x86,0x00]
v_ceil_f32_sdwa v5, src_shared_base dst_sel:DWORD src0_sel:DWORD
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: v_ceil_f32_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xeb,0x16,0xa6,0x00]
v_ceil_f32_sdwa v5, |src_shared_base| dst_sel:DWORD src0_sel:DWORD
@@ -774,7 +782,7 @@ v_ceil_f32_sdwa v5, |src_shared_base| dst_sel:DWORD src0_sel:DWORD
// named inline values compete with other scalars for constant bus access
//---------------------------------------------------------------------------//
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_add_u32 v0, private_base, s0
@@ -783,17 +791,17 @@ v_add_u32 v0, private_base, s0
v_add_u32 v0, scc, s0
// v_div_fmas implicitly reads VCC
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_div_fmas_f32 v0, shared_base, v0, v1
// v_div_fmas implicitly reads VCC
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_div_fmas_f32 v0, v0, shared_limit, v1
// v_div_fmas implicitly reads VCC
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_div_fmas_f32 v0, v0, v1, private_limit
@@ -810,29 +818,29 @@ v_div_fmas_f32 v0, v0, scc, v1
v_div_fmas_f32 v0, v0, v1, vccz
// v_addc_co_u32 implicitly reads VCC (VOP2)
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_addc_co_u32 v0, vcc, shared_base, v0, vcc
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_madak_f32 v0, shared_base, v0, 0x11213141
// NOGCN: error: invalid operand (violates constant bus restrictions)
v_madak_f32 v0, scc, v0, 0x11213141
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_cmp_eq_f32 s[0:1], private_base, private_limit
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_cmp_eq_f32 s[0:1], private_base, s0
// NOGCN: error: invalid operand (violates constant bus restrictions)
v_cmp_eq_f32 s[0:1], execz, s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_pk_add_f16 v255, private_base, private_limit
diff --git a/llvm/test/MC/AMDGPU/mtbuf.s b/llvm/test/MC/AMDGPU/mtbuf.s
index 0653b591d69d..a405a8824df4 100644
--- a/llvm/test/MC/AMDGPU/mtbuf.s
+++ b/llvm/test/MC/AMDGPU/mtbuf.s
@@ -289,7 +289,7 @@ tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]
// Invalid soffset
tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s[255] format:[BUF_NUM_FORMAT_FLOAT]
-// GCN-ERR: error: not a valid operand.
+// GCN-ERR: error: register index is out of range
// Both legacy and symbolic formats are specified
tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], dfmt:1 s0 format:[BUF_NUM_FORMAT_FLOAT]
diff --git a/llvm/test/MC/AMDGPU/out-of-range-registers.s b/llvm/test/MC/AMDGPU/out-of-range-registers.s
index c7cd03470f9f..e350fc5de520 100644
--- a/llvm/test/MC/AMDGPU/out-of-range-registers.s
+++ b/llvm/test/MC/AMDGPU/out-of-range-registers.s
@@ -4,112 +4,108 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX10-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SIVICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=SIVICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefixes=SIVICI,CIVI9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefixes=GFX9,CIVI9 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
s_add_i32 s106, s0, s1
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_add_i32 s104, s0, s1
-// SICIVI9-ERR: error: not a valid operand
+// SICIVI9-ERR: error: register not available on this GPU
// GFX10: s_add_i32 s104, s0, s1 ; encoding:
s_add_i32 s105, s0, s1
-// SICIVI9-ERR: error: not a valid operand
+// SICIVI9-ERR: error: register not available on this GPU
// GFX10: s_add_i32 s105, s0, s1 ; encoding:
v_add_i32 v256, v0, v1
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
v_add_i32 v257, v0, v1
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_mov_b64 s[0:17], -1
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: invalid or unsupported register size
s_mov_b64 s[103:104], -1
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: invalid register alignment
s_mov_b64 s[105:106], -1
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: invalid register alignment
s_mov_b64 s[104:105], -1
-// SICIVI9-ERR: error: not a valid operand
+// SICIVI9-ERR: error: register not available on this GPU
// GFX10: s_mov_b64 s[104:105], -1 ; encoding:
s_load_dwordx4 s[102:105], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: invalid register alignment
s_load_dwordx4 s[104:108], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx4 s[108:112], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx4 s[1:4], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: invalid register alignment
-s_load_dwordx4 s[1:4], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+s_load_dwordx4 s[2:5], s[2:3], s4
+// GCN-ERR: error: invalid register alignment
s_load_dwordx8 s[104:111], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx8 s[100:107], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx8 s[108:115], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx16 s[92:107], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx16 s[96:111], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx16 s[100:115], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx16 s[104:119], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_load_dwordx16 s[108:123], s[2:3], s4
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_mov_b32 ttmp16, 0
-// GCN-ERR: error: not a valid operand
+// GCN-ERR: error: register index is out of range
s_mov_b32 ttmp12, 0
-// SICIVI: error: not a valid operand
// GFX9: s_mov_b32 ttmp12, 0 ; encoding:
// GFX10: s_mov_b32 ttmp12, 0 ; encoding:
-// SIVICI-ERR: error: not a valid operand.
+// SIVICI-ERR: error: register not available on this GPU
s_mov_b32 ttmp15, 0
-// SICIVI: error: not a valid operand
// GFX9: s_mov_b32 ttmp15, 0 ; encoding:
// GFX10: s_mov_b32 ttmp15, 0 ; encoding:
-// SIVICI-ERR: error: not a valid operand.
+// SIVICI-ERR: error: register not available on this GPU
s_mov_b32 flat_scratch_lo, 0
-// SI-ERR: error: not a valid operand
-// CIVI9: s_mov_b32 flat_scratch_lo, 0 ; encoding:
-// GFX10-ERR: error: not a valid operand
-// GFX9: s_mov_b32 flat_scratch_lo, 0 ; encoding: [0x80,0x00,0xe6,0xbe]
+// SI-ERR: error: register not available on this GPU
+// GFX10-ERR: error: register not available on this GPU
+// CIVI9: s_mov_b32 flat_scratch_lo, 0 ; encoding: [0x80,0x00,0xe6,0xbe]
s_mov_b32 flat_scratch_hi, 0
-// SI-ERR: error: not a valid operand
-// CIVI9: s_mov_b32 flat_scratch_hi, 0 ; encoding:
-// GFX10-ERR: error: not a valid operand
-// GFX9: s_mov_b32 flat_scratch_hi, 0 ; encoding: [0x80,0x00,0xe7,0xbe]
+// SI-ERR: error: register not available on this GPU
+// GFX10-ERR: error: register not available on this GPU
+// CIVI9: s_mov_b32 flat_scratch_hi, 0 ; encoding: [0x80,0x00,0xe7,0xbe]
s_mov_b32 tma_lo, 0
// SIVICI: s_mov_b32 tma_lo, 0 ; encoding:
-// GFX9-ERR: error: not a valid operand
-// GFX10-ERR: error: not a valid operand
+// GFX9-ERR: error: register not available on this GPU
+// GFX10-ERR: error: register not available on this GPU
s_mov_b32 tba_lo, 0
// SIVICI: s_mov_b32 tba_lo, 0 ; encoding:
-// GFX9-ERR: error: not a valid operand
-// GFX10-ERR: error: not a valid operand
+// GFX9-ERR: error: register not available on this GPU
+// GFX10-ERR: error: register not available on this GPU
diff --git a/llvm/test/MC/AMDGPU/reg-syntax-err.s b/llvm/test/MC/AMDGPU/reg-syntax-err.s
index dce9375a4711..8f2c3e79310c 100644
--- a/llvm/test/MC/AMDGPU/reg-syntax-err.s
+++ b/llvm/test/MC/AMDGPU/reg-syntax-err.s
@@ -1,73 +1,151 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
s_mov_b32 s1, s 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
s_mov_b32 s1, s[0 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a closing square bracket
s_mov_b32 s1, s[0:0 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a closing square bracket
s_mov_b32 s1, [s[0 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a closing square bracket
s_mov_b32 s1, [s[0:1] 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a single 32-bit register
s_mov_b32 s1, [s0, 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a register or a list of registers
s_mov_b32 s1, s999 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: register index is out of range
s_mov_b32 s1, s[1:2] 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: invalid register alignment
s_mov_b32 s1, s[0:2] 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
s_mov_b32 s1, xnack_mask_lo 1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: register not available on this GPU
s_mov_b32 s1, s s0
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
s_mov_b32 s1, s[0 s0
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a closing square bracket
s_mov_b32 s1, s[0:0 s0
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a closing square bracket
s_mov_b32 s1, [s[0 s0
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a closing square bracket
s_mov_b32 s1, [s[0:1] s0
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: expected a single 32-bit register
s_mov_b32 s1, [s0, s0
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: registers in a list must have consecutive indices
s_mov_b32 s1, s999 s0
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: register index is out of range
s_mov_b32 s1, s[1:2] s0
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: invalid register alignment
s_mov_b32 s1, s[0:2] vcc_lo
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
s_mov_b32 s1, xnack_mask_lo s1
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: register not available on this GPU
exp mrt0 v1, v2, v3, v4000 off
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: register index is out of range
v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: invalid register index
v_add_f64 v[0:1], v[0:1], v[0x1:0xF00000002]
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: invalid register index
s_mov_b32 s1, s[0:-1]
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
+// NOVI: error: invalid register index
+
+s_mov_b64 s[10:11], [exec_lo,vcc_hi]
+// NOVI: error: register does not fit in the list
+
+s_mov_b64 s[10:11], [exec_hi,exec_lo]
+// NOVI: error: register does not fit in the list
+
+s_mov_b64 s[10:11], [exec_lo,exec_lo]
+// NOVI: error: register does not fit in the list
+
+s_mov_b64 s[10:11], [exec,exec_lo]
+// NOVI: error: register does not fit in the list
+
+s_mov_b64 s[10:11], [exec_lo,exec]
+// NOVI: error: register does not fit in the list
+
+s_mov_b64 s[10:11], [exec_lo,s0]
+// NOVI: error: registers in a list must be of the same kind
+
+s_mov_b64 s[10:11], [s0,exec_lo]
+// NOVI: error: registers in a list must be of the same kind
+
+s_mov_b64 s[10:11], [s0,exec]
+// NOVI: error: registers in a list must be of the same kind
+
+s_mov_b64 s[10:11], [s0,v1]
+// NOVI: error: registers in a list must be of the same kind
+
+s_mov_b64 s[10:11], [v0,s1]
+// NOVI: error: registers in a list must be of the same kind
+
+s_mov_b64 s[10:11], [s0,s0]
+// NOVI: error: registers in a list must have consecutive indices
+
+s_mov_b64 s[10:11], [s0,s2]
+// NOVI: error: registers in a list must have consecutive indices
+
+s_mov_b64 s[10:11], [s2,s1]
+// NOVI: error: registers in a list must have consecutive indices
+
+s_mov_b64 s[10:11], [a0,a2]
+// NOVI: error: registers in a list must have consecutive indices
+
+s_mov_b64 s[10:11], [a0,v1]
+// NOVI: error: registers in a list must be of the same kind
+
+s_mov_b64 s[10:11], [s
+// NOVI: error: missing register index
+
+s_mov_b64 s[10:11], s[1:0]
+// NOVI: error: first register index should not exceed second index
+
+s_mov_b64 s[10:11], [x0,s1]
+// NOVI: error: invalid register name
+
+s_mov_b64 s[10:11], [s,s1]
+// NOVI: error: missing register index
+
+s_mov_b64 s[10:11], [s01,s1]
+// NOVI: error: registers in a list must have consecutive indices
+
+s_mov_b64 s[10:11], [s0x]
+// NOVI: error: invalid register index
+
+s_mov_b64 s[10:11], [s[0:1],s[2:3]]
+// NOVI: error: expected a single 32-bit register
+
+s_mov_b64 s[10:11], [s0,s[2:3]]
+// NOVI: error: expected a single 32-bit register
+
+s_mov_b64 s[10:11], [s0
+// NOVI: error: expected a comma or a closing square bracket
+
+s_mov_b64 s[10:11], [s0,s1
+// NOVI: error: expected a comma or a closing square bracket
+
+s_mov_b64 s[10:11], s[1:0]
+// NOVI: error: first register index should not exceed second index
diff --git a/llvm/test/MC/AMDGPU/reg-syntax-extra.s b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
index 528247f56239..1f887118ef8a 100644
--- a/llvm/test/MC/AMDGPU/reg-syntax-extra.s
+++ b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
@@ -38,9 +38,9 @@ s_mov_b64 [exec_lo,exec_hi], s[2:3]
// GFX10: s_mov_b64 exec, s[2:3] ; encoding: [0x02,0x04,0xfe,0xbe]
s_mov_b64 [flat_scratch_lo,flat_scratch_hi], s[2:3]
-// NOSICI: error: not a valid operand.
+// NOSICI: error: register not available on this GPU
// VI: s_mov_b64 flat_scratch, s[2:3] ; encoding: [0x02,0x01,0xe6,0xbe]
-// NOGFX10: error: not a valid operand.
+// NOGFX10: error: register not available on this GPU
s_mov_b64 [vcc_lo,vcc_hi], s[2:3]
// SICI: s_mov_b64 vcc, s[2:3] ; encoding: [0x02,0x04,0xea,0xbe]
@@ -50,12 +50,12 @@ s_mov_b64 [vcc_lo,vcc_hi], s[2:3]
s_mov_b64 [tba_lo,tba_hi], s[2:3]
// SICI: s_mov_b64 tba, s[2:3] ; encoding: [0x02,0x04,0xec,0xbe]
// VI: s_mov_b64 tba, s[2:3] ; encoding: [0x02,0x01,0xec,0xbe]
-// NOGFX10: error: not a valid operand.
+// NOGFX10: error: register not available on this GPU
s_mov_b64 [tma_lo,tma_hi], s[2:3]
// SICI: s_mov_b64 tma, s[2:3] ; encoding: [0x02,0x04,0xee,0xbe]
// VI: s_mov_b64 tma, s[2:3] ; encoding: [0x02,0x01,0xee,0xbe]
-// NOGFX10: error: not a valid operand.
+// NOGFX10: error: register not available on this GPU
v_mov_b32_e32 [v1], [v2]
// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
@@ -151,21 +151,21 @@ flat_load_dwordx4 [v[8/2+4],v9,v[10],v[11/2+6]], v[2:3]
// NOSICI: error: instruction not supported on this GPU
v_mul_f32 v0, null, v2
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI: error: 'null' operand is not supported on this GPU
// GFX10: v_mul_f32_e32 v0, null, v2 ; encoding: [0x7d,0x04,0x00,0x10]
-// NOVI: error: not a valid operand.
+// NOVI: error: 'null' operand is not supported on this GPU
v_mul_f64 v[0:1], null, null
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI: error: 'null' operand is not supported on this GPU
// GFX10: v_mul_f64 v[0:1], null, null ; encoding: [0x00,0x00,0x65,0xd5,0x7d,0xfa,0x00,0x00]
-// NOVI: error: not a valid operand.
+// NOVI: error: 'null' operand is not supported on this GPU
s_add_u32 null, null, null
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI: error: 'null' operand is not supported on this GPU
// GFX10: s_add_u32 null, null, null ; encoding: [0x7d,0x7d,0x7d,0x80]
-// NOVI: error: not a valid operand.
+// NOVI: error: 'null' operand is not supported on this GPU
s_not_b64 s[2:3], null
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI: error: 'null' operand is not supported on this GPU
// GFX10: s_not_b64 s[2:3], null ; encoding: [0x7d,0x08,0x82,0xbe]
-// NOVI: error: not a valid operand.
+// NOVI: error: 'null' operand is not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/smem.s b/llvm/test/MC/AMDGPU/smem.s
index 4d81929b415e..3bae52d64028 100644
--- a/llvm/test/MC/AMDGPU/smem.s
+++ b/llvm/test/MC/AMDGPU/smem.s
@@ -47,12 +47,12 @@ s_memrealtime s[4:5]
s_memrealtime tba
// VI: s_memrealtime tba ; encoding: [0x00,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_memrealtime tma
// VI: s_memrealtime tma ; encoding: [0x80,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_memrealtime ttmp[0:1]
// VI: s_memrealtime ttmp[0:1] ; encoding: [0x00,0x1c,0x94,0xc0,0x00,0x00,0x00,0x00]
@@ -84,22 +84,22 @@ s_store_dword s1, s[2:3], s4 glc
s_store_dword tba_lo, s[2:3], s4
// VI: s_store_dword tba_lo, s[2:3], s4 ; encoding: [0x01,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_store_dword tba_hi, s[2:3], s4
// VI: s_store_dword tba_hi, s[2:3], s4 ; encoding: [0x41,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_store_dword tma_lo, s[2:3], s4
// VI: s_store_dword tma_lo, s[2:3], s4 ; encoding: [0x81,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_store_dword tma_hi, s[2:3], s4
// VI: s_store_dword tma_hi, s[2:3], s4 ; encoding: [0xc1,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
// FIXME: Should error on SI instead of silently ignoring glc
s_load_dword s1, s[2:3], 0xfc glc
@@ -120,22 +120,22 @@ s_buffer_store_dword s10, s[92:95], m0
s_buffer_store_dword tba_lo, s[92:95], m0
// VI: s_buffer_store_dword tba_lo, s[92:95], m0 ; encoding: [0x2e,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_store_dword tba_hi, s[92:95], m0
// VI: s_buffer_store_dword tba_hi, s[92:95], m0 ; encoding: [0x6e,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_store_dword tma_lo, s[92:95], m0
// VI: s_buffer_store_dword tma_lo, s[92:95], m0 ; encoding: [0xae,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_store_dword tma_hi, s[92:95], m0
// VI: s_buffer_store_dword tma_hi, s[92:95], m0 ; encoding: [0xee,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_store_dword ttmp0, s[92:95], m0
// VI: s_buffer_store_dword ttmp0, s[92:95], m0 ; encoding: [0x2e,0x1c,0x60,0xc0,0x7c,0x00,0x00,0x00]
@@ -156,33 +156,32 @@ s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc
s_buffer_store_dwordx2 tba, s[92:95], m0 glc
// VI: s_buffer_store_dwordx2 tba, s[92:95], m0 glc ; encoding: [0x2e,0x1b,0x65,0xc0,0x7c,0x00,0x00,0x00]
// NOSICI: error: invalid operand for instruction
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_load_dword s10, s[92:95], m0
// GFX89: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0x7c,0x5c,0x05,0xc2]
// GFX10: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xf4,0x00,0x00,0x00,0xf8]
-// SICIGFX10: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0x7c,0x5c,0x05,0xc2]
s_buffer_load_dword tba_lo, s[92:95], m0
// VI: s_buffer_load_dword tba_lo, s[92:95], m0 ; encoding: [0x2e,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dword tba_lo, s[92:95], m0 ; encoding: [0x7c,0x5c,0x36,0xc2]
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_load_dword tba_hi, s[92:95], m0
// VI: s_buffer_load_dword tba_hi, s[92:95], m0 ; encoding: [0x6e,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dword tba_hi, s[92:95], m0 ; encoding: [0x7c,0xdc,0x36,0xc2]
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_load_dword tma_lo, s[92:95], m0
// VI: s_buffer_load_dword tma_lo, s[92:95], m0 ; encoding: [0xae,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dword tma_lo, s[92:95], m0 ; encoding: [0x7c,0x5c,0x37,0xc2]
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_load_dword tma_hi, s[92:95], m0
// VI: s_buffer_load_dword tma_hi, s[92:95], m0 ; encoding: [0xee,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dword tma_hi, s[92:95], m0 ; encoding: [0x7c,0xdc,0x37,0xc2]
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_load_dword ttmp0, s[92:95], m0
// VI: s_buffer_load_dword ttmp0, s[92:95], m0 ; encoding: [0x2e,0x1c,0x20,0xc0,0x7c,0x00,0x00,0x00]
@@ -198,12 +197,12 @@ s_buffer_load_dwordx2 s[10:11], s[92:95], m0
s_buffer_load_dwordx2 tba, s[92:95], m0
// VI: s_buffer_load_dwordx2 tba, s[92:95], m0 ; encoding: [0x2e,0x1b,0x24,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dwordx2 tba, s[92:95], m0 ; encoding: [0x7c,0x5c,0x76,0xc2]
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_load_dwordx2 tma, s[92:95], m0
// VI: s_buffer_load_dwordx2 tma, s[92:95], m0 ; encoding: [0xae,0x1b,0x24,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dwordx2 tma, s[92:95], m0 ; encoding: [0x7c,0x5c,0x77,0xc2]
-// NOGFX9: error: not a valid operand.
+// NOGFX9: error: register not available on this GPU
s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0
// VI: s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1c,0x24,0xc0,0x7c,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/smrd-err.s b/llvm/test/MC/AMDGPU/smrd-err.s
index 68f2ac6570c9..5017a1ac59e3 100644
--- a/llvm/test/MC/AMDGPU/smrd-err.s
+++ b/llvm/test/MC/AMDGPU/smrd-err.s
@@ -1,14 +1,14 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti %s | FileCheck -check-prefix=SI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
s_load_dwordx4 s[100:103], s[2:3], s4
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
// SI: s_load_dwordx4 s[100:103], s[2:3], s4
s_load_dwordx8 s[96:103], s[2:3], s4
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
// SI: s_load_dwordx8 s[96:103], s[2:3], s4
s_load_dwordx16 s[88:103], s[2:3], s4
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
// SI: s_load_dwordx16 s[88:103], s[2:3], s4
diff --git a/llvm/test/MC/AMDGPU/smrd.s b/llvm/test/MC/AMDGPU/smrd.s
index 30f01b2ced1c..43819935afd0 100644
--- a/llvm/test/MC/AMDGPU/smrd.s
+++ b/llvm/test/MC/AMDGPU/smrd.s
@@ -105,7 +105,7 @@ s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4
s_load_dwordx4 s[100:103], s[2:3], s4
// GCN: s_load_dwordx4 s[100:103], s[2:3], s4 ; encoding: [0x04,0x02,0xb2,0xc0]
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
s_load_dwordx8 s[8:15], s[2:3], 1
// GCN: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0]
@@ -117,7 +117,7 @@ s_load_dwordx8 s[8:15], s[2:3], s4
s_load_dwordx8 s[96:103], s[2:3], s4
// GCN: s_load_dwordx8 s[96:103], s[2:3], s4 ; encoding: [0x04,0x02,0xf0,0xc0]
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
s_load_dwordx16 s[16:31], s[2:3], 1
// GCN: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1]
@@ -129,7 +129,7 @@ s_load_dwordx16 s[16:31], s[2:3], s4
s_load_dwordx16 s[88:103], s[2:3], s4
// GCN: s_load_dwordx16 s[88:103], s[2:3], s4 ; encoding: [0x04,0x02,0x2c,0xc1]
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
s_buffer_load_dword s1, s[4:7], 1
// GCN: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x01,0x85,0x00,0xc2]
@@ -189,7 +189,7 @@ s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4
s_buffer_load_dwordx4 s[100:103], s[4:7], s4
// GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2]
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
s_buffer_load_dwordx8 s[8:15], s[4:7], 1
// GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x01,0x05,0xc4,0xc2]
@@ -201,7 +201,7 @@ s_buffer_load_dwordx8 s[8:15], s[4:7], s4
s_buffer_load_dwordx8 s[96:103], s[4:7], s4
// GCN: s_buffer_load_dwordx8 s[96:103], s[4:7], s4 ; encoding: [0x04,0x04,0xf0,0xc2]
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
s_buffer_load_dwordx16 s[16:31], s[4:7], 1
// GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x01,0x05,0x08,0xc3]
@@ -213,7 +213,7 @@ s_buffer_load_dwordx16 s[16:31], s[4:7], s4
s_buffer_load_dwordx16 s[88:103], s[4:7], s4
// GCN: s_buffer_load_dwordx16 s[88:103], s[4:7], s4 ; encoding: [0x04,0x04,0x2c,0xc3]
-// NOVI: error: not a valid operand
+// NOVI: error: register not available on this GPU
s_dcache_inv
// GCN: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
diff --git a/llvm/test/MC/AMDGPU/sop1-err.s b/llvm/test/MC/AMDGPU/sop1-err.s
index 6322f5b098c3..fe2a02154106 100644
--- a/llvm/test/MC/AMDGPU/sop1-err.s
+++ b/llvm/test/MC/AMDGPU/sop1-err.s
@@ -9,16 +9,16 @@ s_mov_b32 s1, v0
// GCN: error: invalid operand for instruction
s_mov_b32 s[1:2], s0
-// GCN: error: not a valid operand
+// GCN: error: invalid register alignment
s_mov_b32 s0, s[1:2]
-// GCN: error: not a valid operand
+// GCN: error: invalid register alignment
s_mov_b32 s220, s0
-// GCN: error: not a valid operand
+// GCN: error: register index is out of range
s_mov_b32 s0, s220
-// GCN: error: not a valid operand
+// GCN: error: register index is out of range
s_mov_b64 s1, s[0:1]
// GCN: error: invalid operand for instruction
@@ -32,13 +32,10 @@ s_mov_b32 s
// Out of range register
s_mov_b32 s102, 1
-// VI: error: not a valid operand
-// SI: s_mov_b32 s102, 1
+// VI: error: register not available on this GPU
s_mov_b32 s103, 1
-// VI: error: not a valid operand
-// SI: s_mov_b32 s103, 1
+// VI: error: register not available on this GPU
s_mov_b64 s[102:103], -1
-// VI: error: not a valid operand
-// SI: s_mov_b64 s[102:103], -1
+// VI: error: register not available on this GPU
diff --git a/llvm/test/MC/AMDGPU/sop1.s b/llvm/test/MC/AMDGPU/sop1.s
index dafbf650b671..3b0bafd4ae2c 100644
--- a/llvm/test/MC/AMDGPU/sop1.s
+++ b/llvm/test/MC/AMDGPU/sop1.s
@@ -42,8 +42,8 @@ s_mov_b64 s[2:3], s[4:5]
s_mov_b64 null, s[4:5]
// GFX10: s_mov_b64 null, s[4:5] ; encoding: [0x04,0x04,0xfd,0xbe]
-// NOSICIVI: error: not a valid operand.
-// NOGFX9: error: not a valid operand.
+// NOSICIVI: error: 'null' operand is not supported on this GPU
+// NOGFX9: error: 'null' operand is not supported on this GPU
s_mov_b64 s[2:3], 0xffffffffffffffff
// SICI: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x04,0x82,0xbe]
@@ -62,7 +62,7 @@ s_mov_b64 s[0:1], 0x80000000
s_mov_b64 s[102:103], -1
// SICI: s_mov_b64 s[102:103], -1 ; encoding: [0xc1,0x04,0xe6,0xbe]
-// NOGFX89: error: not a valid operand
+// NOGFX89: error: register not available on this GPU
// GFX10: s_mov_b64 s[102:103], -1 ; encoding: [0xc1,0x04,0xe6,0xbe]
s_cmov_b32 s1, 200
diff --git a/llvm/test/MC/AMDGPU/sop2.s b/llvm/test/MC/AMDGPU/sop2.s
index 89f41a7b3d51..94152bd98695 100644
--- a/llvm/test/MC/AMDGPU/sop2.s
+++ b/llvm/test/MC/AMDGPU/sop2.s
@@ -65,8 +65,8 @@ s_and_b32 s2, 0xFFFF0000, -65536
s_and_b64 null, s[4:5], s[6:7]
// GFX10: s_and_b64 null, s[4:5], s[6:7] ; encoding: [0x04,0x06,0xfd,0x87]
-// NOSICIVI: error: not a valid operand.
-// NOGFX9: error: not a valid operand.
+// NOSICIVI: error: 'null' operand is not supported on this GPU
+// NOGFX9: error: 'null' operand is not supported on this GPU
s_and_b64 s[2:3], s[4:5], s[6:7]
// SICI: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87]
@@ -235,7 +235,7 @@ s_abs
diff _i32 s2, s4, s6
s_add_u32 s101, s102, s103
// SICI: s_add_u32 s101, s102, s103 ; encoding: [0x66,0x67,0x65,0x80]
-// NOGFX89: error: not a valid operand
+// NOGFX89: error: register not available on this GPU
// GFX10: s_add_u32 s101, s102, s103 ; encoding: [0x66,0x67,0x65,0x80]
s_lshl1_add_u32 s5, s1, s2
diff --git a/llvm/test/MC/AMDGPU/sopk.s b/llvm/test/MC/AMDGPU/sopk.s
index e128df94c611..14523dcec856 100644
--- a/llvm/test/MC/AMDGPU/sopk.s
+++ b/llvm/test/MC/AMDGPU/sopk.s
@@ -19,74 +19,92 @@ s_movk_i32 s2, 0x6
s_cmovk_i32 s2, 0x6
// SICI: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
// VI9: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb0]
+// GFX10: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
s_cmpk_eq_i32 s2, 0x6
// SICI: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]
// VI9: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
+// GFX10: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]
s_cmpk_lg_i32 s2, 0x6
// SICI: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]
// VI9: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]
+// GFX10: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]
s_cmpk_gt_i32 s2, 0x6
// SICI: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]
// VI9: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]
+// GFX10: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]
s_cmpk_ge_i32 s2, 0x6
// SICI: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]
// VI9: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]
+// GFX10: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]
s_cmpk_lt_i32 s2, 0x6
// SICI: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]
// VI9: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]
+// GFX10: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]
s_cmpk_le_i32 s2, 0x6
// SICI: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]
// VI9: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]
+// GFX10: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]
s_cmpk_eq_u32 s2, 0x6
// SICI: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]
// VI9: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]
+// GFX10: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]
s_cmpk_lg_u32 s2, 0x6
// SICI: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]
// VI9: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]
+// GFX10: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]
s_cmpk_gt_u32 s2, 0x6
// SICI: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]
// VI9: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]
+// GFX10: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]
s_cmpk_ge_u32 s2, 0x6
// SICI: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]
// VI9: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]
+// GFX10: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]
s_cmpk_lt_u32 s2, 0x6
// SICI: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]
// VI9: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]
+// GFX10: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]
s_cmpk_le_u32 s2, 0x6
// SICI: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]
// VI9: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]
+// GFX10: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]
s_cmpk_le_u32 s2, 0xFFFF
// SICI: s_cmpk_le_u32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb7]
// VI9: s_cmpk_le_u32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb6]
+// GFX10: s_cmpk_le_u32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb7]
s_addk_i32 s2, 0x6
// SICI: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
// VI9: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]
+// GFX10: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
s_mulk_i32 s2, 0x6
// SICI: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
// VI9: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
+// GFX10: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
s_mulk_i32 s2, -1
// SICI: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]
// VI9: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]
+// GFX10: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]
s_mulk_i32 s2, 0xFFFF
// SICI: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]
// VI9: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]
+// GFX10: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]
s_cbranch_i_fork s[2:3], 0x6
// SICI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x82,0xb8]
@@ -100,26 +118,31 @@ s_cbranch_i_fork s[2:3], 0x6
s_getreg_b32 s2, 0x6
// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
// HW register identifier, non-default offset/width
s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31)
// SICI: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x02,0xb9]
// HW register code of unknown HW register, non-default offset/width
s_getreg_b32 s2, hwreg(51, 1, 31)
// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]
// HW register code of unknown HW register, default offset/width
s_getreg_b32 s2, hwreg(51)
// SICI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9]
// HW register code of unknown HW register, valid symbolic name range but no name available
s_getreg_b32 s2, hwreg(10)
// SICI: s_getreg_b32 s2, hwreg(10) ; encoding: [0x0a,0xf8,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(10) ; encoding: [0x0a,0xf8,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(10) ; encoding: [0x0a,0xf8,0x02,0xb9]
// HW_REG_SH_MEM_BASES valid starting from GFX9
s_getreg_b32 s2, hwreg(15)
@@ -183,31 +206,37 @@ s_getreg_b32 s2, hwreg(25)
s_setreg_b32 0x6, s2
// SICI: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]
+// GFX10: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x82,0xb9]
// raw number mapped to unknown HW register
s_setreg_b32 0x33, s2
// SICI: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x02,0xb9]
+// GFX10: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x82,0xb9]
// raw number mapped to known HW register, default offset/width
s_setreg_b32 0xf803, s2
// SICI: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x02,0xb9]
+// GFX10: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x82,0xb9]
// HW register identifier, default offset/width implied
s_setreg_b32 hwreg(HW_REG_HW_ID), s2
// SICI: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x02,0xb9]
+// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x82,0xb9]
// HW register identifier, non-default offset/width
s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2
// SICI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x02,0xb9]
+// GFX10: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]
// HW register code of unknown HW register, valid symbolic name range but no name available
s_setreg_b32 hwreg(10), s2
// SICI: s_setreg_b32 hwreg(10), s2 ; encoding: [0x0a,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(10), s2 ; encoding: [0x0a,0xf8,0x02,0xb9]
+// GFX10: s_setreg_b32 hwreg(10), s2 ; encoding: [0x0a,0xf8,0x82,0xb9]
// HW_REG_SH_MEM_BASES valid starting from GFX9
s_setreg_b32 hwreg(15), s2
@@ -271,16 +300,19 @@ s_setreg_b32 hwreg(25), s2
s_setreg_b32 hwreg(5, 1, 31), s2
// SICI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x02,0xb9]
+// GFX10: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9]
// raw number mapped to known HW register
s_setreg_imm32_b32 0x6, 0xff
// SICI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
// VI9: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
+// GFX10: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
// HW register identifier, non-default offset/width
s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff
// SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]
// VI9: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
+// GFX10: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]
//===----------------------------------------------------------------------===//
// expressions and hwreg macro
@@ -290,16 +322,19 @@ hwreg=6
s_getreg_b32 s2, hwreg
// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
x=5
s_getreg_b32 s2, x+1
// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
x=5
s_getreg_b32 s2, 1+x
// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
reg=50
offset=2
@@ -307,10 +342,12 @@ width=30
s_getreg_b32 s2, hwreg(reg + 1, offset - 1, width + 1)
// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]
s_getreg_b32 s2, hwreg(1 + reg, -1 + offset, 1 + width)
// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]
// VI9: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
+// GFX10: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]
//===----------------------------------------------------------------------===//
// Instructions
@@ -319,30 +356,36 @@ s_getreg_b32 s2, hwreg(1 + reg, -1 + offset, 1 + width)
s_endpgm_ordered_ps_done
// GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
// NOSICIVI: error: instruction not supported on this GPU
+// GFX10: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
s_call_b64 null, 12609
// GFX10: s_call_b64 null, 12609 ; encoding: [0x41,0x31,0x7d,0xbb]
-// NOSICIVI: error: not a valid operand.
-// NOGFX9: error: not a valid operand.
+// NOSICIVI: error: 'null' operand is not supported on this GPU
+// NOGFX9: error: 'null' operand is not supported on this GPU
s_call_b64 s[12:13], 12609
// GFX9: s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x8c,0xba]
// NOSICIVI: error: instruction not supported on this GPU
+// GFX10: s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x0c,0xbb]
s_call_b64 s[100:101], 12609
// GFX9: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0xe4,0xba]
// NOSICIVI: error: instruction not supported on this GPU
+// GFX10: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0x64,0xbb]
s_call_b64 s[10:11], 49617
// GFX9: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x8a,0xba]
// NOSICIVI: error: instruction not supported on this GPU
+// GFX10: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x0a,0xbb]
offset = 4
s_call_b64 s[0:1], offset + 4
// GFX9: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x80,0xba]
// NOSICIVI: error: instruction not supported on this GPU
+// GFX10: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x00,0xbb]
offset = 4
s_call_b64 s[0:1], 4 + offset
// GFX9: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x80,0xba]
// NOSICIVI: error: instruction not supported on this GPU
+// GFX10: s_call_b64 s[0:1], 8 ; encoding: [0x08,0x00,0x00,0xbb]
diff --git a/llvm/test/MC/AMDGPU/trap.s b/llvm/test/MC/AMDGPU/trap.s
index 5d23c1f30d6e..18296c859642 100644
--- a/llvm/test/MC/AMDGPU/trap.s
+++ b/llvm/test/MC/AMDGPU/trap.s
@@ -20,124 +20,124 @@ s_add_u32 ttmp0, ttmp0, 4
s_add_u32 ttmp4, 8, ttmp4
// SICI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
// VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
-// GXF9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
+// GFX9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
s_add_u32 ttmp4, ttmp4, 0x00000100
// SICI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
// VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
-// GXF9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
+// GFX9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
s_add_u32 ttmp4, ttmp4, 4
// SICI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
// VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
-// GXF9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
+// GFX9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
s_add_u32 ttmp4, ttmp8, ttmp4
// SICI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
// VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
-// GXF9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
+// GFX9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
s_and_b32 ttmp10, ttmp8, 0x00000080
// SICI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x87,0x80,0x00,0x00,0x00]
// VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
-// GXF9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x74,0x86,0x80,0x00,0x00,0x00]
+// GFX9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x76,0x86,0x80,0x00,0x00,0x00]
s_and_b32 ttmp9, tma_hi, 0x0000ffff
// SICI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x87,0xff,0xff,0x00,0x00]
// VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
-// NOGFX9: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
s_and_b32 ttmp9, ttmp9, 0x000001ff
// SICI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x87,0xff,0x01,0x00,0x00]
// VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
-// GXF9: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
+// GFX9: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
s_and_b32 ttmp9, tma_lo, 0xffff0000
// SICI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x87,0x00,0x00,0xff,0xff]
// VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
-// NOGFX9: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
s_and_b32 ttmp9, ttmp9, ttmp8
// SICI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x87]
// VI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x86]
-// GXF9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x78,0x75,0x86]
+// GFX9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x74,0x75,0x86]
s_and_b32 ttmp8, ttmp1, 0x01000000
// SICI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x87,0x00,0x00,0x00,0x01]
// VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
-// GXF9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
+// GFX9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
s_cmp_eq_i32 ttmp8, 0
// SICI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
// VI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
-// GXF9: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x74,0x80,0x00,0xbf]
+// GFX9: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x74,0x80,0x00,0xbf]
s_cmp_eq_i32 ttmp8, 0x000000fe
// SICI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
// VI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
-// GXF9: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
+// GFX9: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
s_lshr_b32 ttmp8, ttmp8, 12
// SICI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x90]
// VI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x8f]
-// GXF9: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x74,0x8c,0x74,0x8f]
+// GFX9: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x74,0x8c,0x74,0x8f]
v_mov_b32_e32 v1, ttmp8
// SICI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
// VI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
-// GXF9: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x74,0x02,0x02,0x7e]
+// GFX9: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x74,0x02,0x02,0x7e]
s_mov_b32 m0, ttmp8
// SICI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x03,0xfc,0xbe]
// VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe]
-// GXF9: s_mov_b32 m0, ttmp8 ; encoding: [0x74,0x00,0xfc,0xbe]
+// GFX9: s_mov_b32 m0, ttmp8 ; encoding: [0x74,0x00,0xfc,0xbe]
s_mov_b32 ttmp10, 0
// SICI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x03,0xfa,0xbe]
// VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe]
-// GXF9: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xf6,0xbe]
+// GFX9: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xf6,0xbe]
s_mov_b32 ttmp11, 0x01024fac
// SICI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x03,0xfb,0xbe,0xac,0x4f,0x02,0x01]
// VI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
-// GXF9: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
+// GFX9: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
s_mov_b32 ttmp8, m0
// SICI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x03,0xf8,0xbe]
// VI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf8,0xbe]
-// GXF9: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf4,0xbe]
+// GFX9: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf4,0xbe]
s_mov_b32 ttmp8, tma_lo
// SICI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x03,0xf8,0xbe]
// VI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x00,0xf8,0xbe]
-// NOGFX9: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
s_mul_i32 ttmp8, 0x00000324, ttmp8
// SICI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x93,0x24,0x03,0x00,0x00]
// VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
-// GXF9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
+// GFX9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
s_or_b32 ttmp9, ttmp9, 0x00280000
// SICI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x88,0x00,0x00,0x28,0x00]
// VI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
-// GXF9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
+// GFX9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
// ttmp12..ttmp15 (GFX9 only)
s_add_u32 ttmp0, ttmp12, 4
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
s_add_u32 ttmp0, ttmp13, 4
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
s_add_u32 ttmp0, ttmp14, 4
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
s_add_u32 ttmp0, ttmp15, 4
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
//===----------------------------------------------------------------------===//
@@ -162,31 +162,31 @@ s_mov_b64 exec, [ttmp4,ttmp5]
s_mov_b64 tba, ttmp[4:5]
// SICI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x04,0xec,0xbe]
// VI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x01,0xec,0xbe]
-// NOGFX9: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
s_mov_b64 ttmp[4:5], tba
// SICI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x01,0xf4,0xbe]
-// NOGFX9: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
s_mov_b64 tma, ttmp[4:5]
// SICI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x04,0xee,0xbe]
// VI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x01,0xee,0xbe]
-// NOGFX9: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
s_mov_b64 ttmp[4:5], tma
// SICI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x04,0xf4,0xbe]
// VI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x01,0xf4,0xbe]
-// NOGFX9: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
// ttmp12..ttmp15 (GFX9 only)
s_mov_b64 ttmp[12:13], exec
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_mov_b64 ttmp[12:13], exec ; encoding: [0x7e,0x01,0xf8,0xbe]
s_mov_b64 ttmp[14:15], exec
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: s_mov_b64 ttmp[14:15], exec ; encoding: [0x7e,0x01,0xfa,0xbe]
//===----------------------------------------------------------------------===//
@@ -197,25 +197,29 @@ s_mov_b64 ttmp[14:15], exec
s_buffer_load_dwordx8 ttmp[0:7], s[0:3], s0
// VI: [0x00,0x1c,0x2c,0xc0,0x00,0x00,0x00,0x00]
// GFX9: [0x00,0x1b,0x2c,0xc0,0x00,0x00,0x00,0x00]
+// SICI: s_buffer_load_dwordx8 ttmp[0:7], s[0:3], s0 ; encoding: [0x00,0x00,0xf8,0xc2]
s_buffer_load_dwordx8 ttmp[4:11], s[0:3], s0
// VI: [0x00,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00]
// GFX9: [0x00,0x1c,0x2c,0xc0,0x00,0x00,0x00,0x00]
+// SICI: s_buffer_load_dwordx8 ttmp[4:11], s[0:3], s0 ; encoding: [0x00,0x00,0xfa,0xc2]
s_buffer_load_dwordx8 ttmp[8:15], s[0:3], s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: [0x00,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00]
s_load_dwordx8 ttmp[0:7], s[0:1], s0
// VI: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
// GFX9: [0x00,0x1b,0x0c,0xc0,0x00,0x00,0x00,0x00]
+// SICI: s_load_dwordx8 ttmp[0:7], s[0:1], s0 ; encoding: [0x00,0x00,0xf8,0xc0]
s_load_dwordx8 ttmp[4:11], s[0:1], s0
// VI: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
// GFX9: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
+// SICI: s_load_dwordx8 ttmp[4:11], s[0:1], s0 ; encoding: [0x00,0x00,0xfa,0xc0]
s_load_dwordx8 ttmp[8:15], s[0:1], s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
//===----------------------------------------------------------------------===//
@@ -224,11 +228,11 @@ s_load_dwordx8 ttmp[8:15], s[0:1], s0
//===----------------------------------------------------------------------===//
s_buffer_load_dwordx16 ttmp[0:15], s[0:3], s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: [0x00,0x1b,0x30,0xc0,0x00,0x00,0x00,0x00]
s_load_dwordx16 ttmp[0:15], s[0:1], s0
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: [0x00,0x1b,0x10,0xc0,0x00,0x00,0x00,0x00]
//===----------------------------------------------------------------------===//
@@ -253,5 +257,5 @@ buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
// ttmp12..ttmp15 (GFX9 only)
buffer_atomic_inc v1, off, ttmp[12:15], 56 glc
-// NOSICIVI: error: not a valid operand
+// NOSICIVI: error: register not available on this GPU
// GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
diff --git a/llvm/test/MC/AMDGPU/vop3.s b/llvm/test/MC/AMDGPU/vop3.s
index e5ff3f030a6f..2c083e7024e3 100644
--- a/llvm/test/MC/AMDGPU/vop3.s
+++ b/llvm/test/MC/AMDGPU/vop3.s
@@ -289,17 +289,17 @@ v_mac_f32_e64 v0, -v1, |v2|
v_mac_f16_e64 v0, 0.5, flat_scratch_lo
// VI: v_mac_f16_e64 v0, 0.5, flat_scratch_lo ; encoding: [0x00,0x00,0x23,0xd1,0xf0,0xcc,0x00,0x00]
// NOCI: error: instruction not supported on this GPU
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
v_mac_f16_e64 v0, -4.0, flat_scratch_lo
// VI: v_mac_f16_e64 v0, -4.0, flat_scratch_lo ; encoding: [0x00,0x00,0x23,0xd1,0xf7,0xcc,0x00,0x00]
// NOCI: error: instruction not supported on this GPU
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
v_mac_f16_e64 v0, flat_scratch_lo, -4.0
// VI: v_mac_f16_e64 v0, flat_scratch_lo, -4.0 ; encoding: [0x00,0x00,0x23,0xd1,0x66,0xee,0x01,0x00]
// NOCI: error: instruction not supported on this GPU
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
v_add_u32 v84, vcc, v13, s31 clamp
// NOSICI: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/vop_sdwa.s b/llvm/test/MC/AMDGPU/vop_sdwa.s
index 88386e046917..9a4283e73e38 100644
--- a/llvm/test/MC/AMDGPU/vop_sdwa.s
+++ b/llvm/test/MC/AMDGPU/vop_sdwa.s
@@ -717,8 +717,8 @@ v_mov_b32 v1, s2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
// GFX9: v_mov_b32_sdwa v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x7e,0x10,0x86,0x00]
v_mov_b32 v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// NOSICI: error: not a valid operand.
-// NOVI: error: not a valid operand.
+// NOSICI: error: register not available on this GPU
+// NOVI: error: register not available on this GPU
// GFX9: v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x00]
v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
@@ -735,19 +735,16 @@ v_add_f32 v0, v0, s22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_s
// NOSICI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
// NOGFX9: error: invalid operand for instruction
-// NO: invalid operand (violates constant bus restrictions)
v_add_f32 v0, exec_lo, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
-// NOGFX9: error: not a valid operand.
-// NO: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
v_add_f32 v0, v1, tba_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
-// NOGFX9: error: not a valid operand.
-// NO: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
v_add_f32 v0, v1, tma_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: invalid operand for instruction
@@ -760,25 +757,23 @@ v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
// GFX9: v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x84,0x7c,0x01,0x00,0x05,0x82]
v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2
-// NOSICI: error: not a valid operand.
-// NOVI: error: not a valid operand.
+// NOSICI: error: register not available on this GPU
+// NOVI: error: register not available on this GPU
// GFX9: v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02]
v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: invalid operand for instruction
// NOVI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
-// NO: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
v_cmp_eq_f32_sdwa tba, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: invalid operand for instruction
// NOVI: error: instruction not supported on this GPU
-// NOGFX9: error: not a valid operand.
-// NO: error: not a valid operand
+// NOGFX9: error: register not available on this GPU
v_cmp_eq_f32_sdwa tma, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
-// NOSICI: error: not a valid operand.
-// NOVI: error: not a valid operand.
+// NOSICI: error: register not available on this GPU
+// NOVI: error: register not available on this GPU
// GFX9: v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82]
v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2
@@ -789,7 +784,7 @@ v_cmp_eq_f32_sdwa vcc, exec_lo, vcc_lo src0_sel:WORD_1 src1_sel:BYTE_2
// NOVI: error: invalid operand for instruction
// GFX9: v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0x66,0x06,0x86,0x00]
-// NOSI: error: not a valid operand.
+// NOSI: error: register not available on this GPU
// NOCI: error: not a valid operand.
v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
diff --git a/llvm/test/MC/AMDGPU/xnack-mask.s b/llvm/test/MC/AMDGPU/xnack-mask.s
index 0fa5242d3789..e6e310724d45 100644
--- a/llvm/test/MC/AMDGPU/xnack-mask.s
+++ b/llvm/test/MC/AMDGPU/xnack-mask.s
@@ -7,25 +7,25 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -show-encoding %s | FileCheck -check-prefix=XNACK %s
s_mov_b64 xnack_mask, -1
-// NOSICIVI10: error: not a valid operand.
+// NOSICIVI10: error: register not available on this GPU
// XNACK: s_mov_b64 xnack_mask, -1 ; encoding: [0xc1,0x01,0xe8,0xbe]
s_mov_b32 xnack_mask_lo, -1
-// NOSICIVI10: error: not a valid operand.
+// NOSICIVI10: error: register not available on this GPU
// XNACK: s_mov_b32 xnack_mask_lo, -1 ; encoding: [0xc1,0x00,0xe8,0xbe]
s_mov_b32 xnack_mask_hi, -1
-// NOSICIVI10: error: not a valid operand.
+// NOSICIVI10: error: register not available on this GPU
// XNACK: s_mov_b32 xnack_mask_hi, -1 ; encoding: [0xc1,0x00,0xe9,0xbe]
s_mov_b32 xnack_mask, -1
-// NOSICIVI10: error: not a valid operand.
+// NOSICIVI10: error: register not available on this GPU
// XNACKERR: error: invalid operand for instruction
s_mov_b64 xnack_mask_lo, -1
-// NOSICIVI10: error: not a valid operand.
+// NOSICIVI10: error: register not available on this GPU
// XNACKERR: error: invalid operand for instruction
s_mov_b64 xnack_mask_hi, -1
-// NOSICIVI10: error: not a valid operand.
+// NOSICIVI10: error: register not available on this GPU
// XNACKERR: error: invalid operand for instruction
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