[PATCH] D87114: [AIX][ExecutionEngine] Disable eh frame support when building with Clang on AIX
David Tenty via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 07:08:33 PDT 2020
daltenty updated this revision to Diff 290476.
daltenty added a comment.
- Adjust so we don't alter the MVS case
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D87114/new/
https://reviews.llvm.org/D87114
Files:
llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
llvm/lib/ExecutionEngine/RuntimeDyld/RTDyldMemoryManager.cpp
Index: llvm/lib/ExecutionEngine/RuntimeDyld/RTDyldMemoryManager.cpp
===================================================================
--- llvm/lib/ExecutionEngine/RuntimeDyld/RTDyldMemoryManager.cpp
+++ llvm/lib/ExecutionEngine/RuntimeDyld/RTDyldMemoryManager.cpp
@@ -33,8 +33,9 @@
// Determine whether we can register EH tables.
#if (defined(__GNUC__) && !defined(__ARM_EABI__) && !defined(__ia64__) && \
- !(defined(_AIX) && defined(__ibmxl__)) && !defined(__MVS__) && \
- !defined(__SEH__) && !defined(__USING_SJLJ_EXCEPTIONS__))
+ !(defined(_AIX) && (defined(__ibmxl__) || defined(__clang__))) && \
+ !defined(__MVS__) && !defined(__SEH__) && \
+ !defined(__USING_SJLJ_EXCEPTIONS__))
#define HAVE_EHTABLE_SUPPORT 1
#else
#define HAVE_EHTABLE_SUPPORT 0
Index: llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
===================================================================
--- llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
+++ llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
@@ -631,8 +631,9 @@
// Determine whether we can register EH tables.
#if (defined(__GNUC__) && !defined(__ARM_EABI__) && !defined(__ia64__) && \
- !(defined(_AIX) && defined(__ibmxl__)) && !defined(__MVS__) && \
- !defined(__SEH__) && !defined(__USING_SJLJ_EXCEPTIONS__))
+ !(defined(_AIX) && (defined(__ibmxl__) || defined(__clang__))) && \
+ !defined(__MVS__) && !defined(__SEH__) && \
+ !defined(__USING_SJLJ_EXCEPTIONS__))
#define HAVE_EHTABLE_SUPPORT 1
#else
#define HAVE_EHTABLE_SUPPORT 0
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