[PATCH] D87145: [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/test/CodeGen/X86/masked_store_trunc_usat.ll:5199
+; SSE2-NEXT:    pminsw %xmm9, %xmm0
+; SSE2-NEXT:    pand %xmm8, %xmm0
 ; SSE2-NEXT:    packuswb %xmm1, %xmm0
----------------
RKSimon wrote:
> regression?
Wel, yes... It has spotted that the result of the pminsw is always negative, so rather than XOR with 0x8000 to flip (i.e. clear) the sign bit, it can AND with 0x7fff to clear the sign bit. But unfortunately that means materialising another constant.

I don't know where this XOR -> AND "optimization" happens, or whether it can be finessed.

The other regressions you pointed out below are basically the same issue.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87145/new/

https://reviews.llvm.org/D87145